Hardent Inc.

Member since 2015

Hardent is a professional services firm providing electronic design services, training solutions, and IP products to leading electronics equipment and component manufacturers throughout the world. Hardent works across a wide variety of industries to develop high-complexity electronic products, improve engineering processes, accelerate products' time-to-market and provide expert training solutions.

Electronic Design Services
Hardent's team of experienced electronic design engineers bring customers the skills and specializations needed to quickly get over technical hurdles and send products to market. Our areas of expertise include FPGA/ASIC design and verification, embedded system design, Digital Signal Processing (DSP) design, embedded software development, system hardware design and power/signal integrity analysis. 
 
Our service offering comprises:
 
• Engineering engagements 
• Subject Matter Experts
• Process & methodology consulting (platform implementation)
• Management consulting (strategic & operational planning)
 
Technical Training Solutions
Hardent is the Xilinx Authorized Training Provider (ATP) for Canada, New England and the Southeastern United States, as well as an ARM Approved Training Center for North America. Training courses cover FPGA design, digital signal processing design, embedded software, functional verification, and much more. Training is available online or in-person and is taught by industry experts with real-world engineering experience.
 
IP Products
Hardent’s IP portfolio offers customers ready-made solutions to accelerate product development and meet demanding time-to-market schedules. IP products include VESA Display Stream Compression (DSC) compliant encoder and decoder IP cores for use in ultra high-denition (UHD) applications where visually lossless and ultra-low latency display compression is required.

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Hardent Inc. Product Information

 

VESA DSC Encoder & Decoder IP Cores 
  •  Fully compliant with VESA DSC 1.1
  •  Supports all DSC 1.1 mandatory and optional encoding mechanisms
  • MMAP, BP, MPP and ICH
  •  Buffering compatible with transport stream over video interfaces
  •  Maximum display resolutions
  • 4K (4096 x 2160p)                   
  • 5K UHD+
  • 8K FUHD
  •  Scalable number of parallel hard slice instances (1, 2 or 4)
  •  8 and 10 bits video components
  •  RGB 4:4:4 and yCbCr video I/O format
  •  3 pixels / clock internal processing decoder architecture
  •  1 pixel / clock internal processing  encoder architecture
  •  Optional DSC features can be disabled to improve area (decoder only)
  •  Verified against the VESA DSC 1.1 C model using a comprehensive test image library

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