HDL Design House

Member since 2010

HDLDesign House delivers leading-edge digital and analog, design and verification services and products in numerous areas of SoC and complex FPGA designs. The company develops IP cores and provides complete design and verification services for complex SoC projects. The company also delivers component (VITAL) models for major SoC product developers. Dedicated to fulfilling each customer's unique requirement, HDL Design House has established a reputation as a reliable partner with high-quality products and services, flexible licensing models, competitive pricing and responsible technical support. The company enables customers to concentrate on system-level work and be confident that the various system components have been fully and reliably engineered and tested.

Founded in 2001, HDLDesign House has 60 employees in two design centers – in Belgrade and Cuprija (Serbia). The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS), thereby meeting United Kingdom Accreditation Service (UKAS) regulatory requirements. With ISO 27001:2005 certification, the highest certification standard for information security available, HDLDesign House becomes the first company in Serbia to comply with this standard. In 2006 the company was awarded the SME Exporter of the Year by  Serbia Investment and Export Promotion Agency (SIEPA). 

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HDL Design House Product Information

About FlexIP core library

The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (DSI, UniPro, CSI, M-PHY, D-PHY, DigRF, SlimBus), UFS, I2S, Serial RapidIO, SPI flash memory, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services,customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html

 

MIPI CSI-2 Transmitter IP Core (HIP 3900)

CSI-2 (Camera Serial Interface) transmitter IP core (HIP 3900) is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs pixel packing in form of long packets and short packets, and sends them via PPI interface to the Host processor. HIP 3900 is compliant with the following specifications: CSI-2 (Camera Serial Interface) version 1.01, D-PHY version 1.0, AMBA3 AHB-Lite Protocol Specification version 1.0. . The PPI interface is used to transmit pixel and command from external D-PHY, using independent High Speed (HS) and Low Power (LP) TX data paths. When in LP mode, the CSI-2 Transmitter IP core is used for Ultra Low Power control. In HS mode, the data is received using between 1 and 4 data lanes. Camera Pixel Interface is used to directly connect Camera sensor with CSI-2 Transmitter IP Core. HDL Design House CSI-2 Transmitter IP core (HIP 3900) supports up to 4 data lanes, one clock lane and up to 4 virtual channels. HIP 3900 supports High Speed, Low Power and Ultra Low Power modes. It supports various pixel formats defined in CSI protocol version 1.01: YUV420 8-bit, YUV420 8-bit (legacy), YUV420 10-bit, YUV422 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit (CSPS), YUV422 8-bit, YUV422 10-bit, RGB888, RGB666, RGB565, RGB555, RGB444,RAW6, RAW7,RAW8, RAW10, RAW12, RAW14.

 

MIPI DSI Host IP core (HIP 3500)

HDL Design House MIPI DSI Host IP core (HIP 3500) is a configurable digital core, compliant with the MIPI Alliance DSI specification, providing a high-speed serial interface between an application processor and MIPI DSI compliant display. It supports MIPI DSI protocol version 1.1, MIPI DCS version 1.0, MIPI DBI version 2.0, MIPI DPI version 2.0, MIPI D-PHY version 1.0. The HIP 3500 is fully compliant with AMBA AHB Version 2.0 Compliant Slave Interface. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits (a.k.a. RGB565, RGB666, RGB888).

 

MIPI DSI Peripheral IP core (HIP 3510)

HDL Design House MIPI DSI Periph (Device) IP core (HIP 3510) receives pixel data and commands from host processor through D-PHY interface and sends data to DPI or DBI interfaces. HIP 3510 is a highly configurable digital IP core, supporting 1 to 4 data lanes. The HIP 3510 is fully compliant to MIPI Alliance's DSI, MIPI DBI version 2.0, DPI version 2.0, and DCS standards, as well as to AMBA's AHB specification. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits, (a.k.a. RGB565, RGB666, RGB888). It supports both command and video modes of operation.

 

MIPI D-PHY Receiver IP core (HIPA 10100)

HDL Design House MIPI D-PHY provides a synchronous connection between MIPI D-PHY master (Tx) and slave (Rx) sides. This IP core performs receive function of D-PHY protocol. D-PHY configuration consists of one Clock Lane and up to 4 Data Lanes. The number of Data Lanes is configurable. Typical D-PHY receiver consists of one D-PHY Rx Clock Lane Module and as many D-PHY Rx Data Lane Modules as there are data lanes. Each Lane consists of an analog front end to generate electrical levels, detects signals from interconnects and translate them into digital values and control and interface logic to control I/O functions. D-PHY is silicon proven with production level status in 65nm and 40nm nodes.

 

MIPI D-PHY Transmitter IP core (HIPA 10000)

D-PHY provides a synchronous connection between MIPI D-PHY master (Tx) and slave (Rx) sides. This IP core performs transmit function of D-PHY protocol. PHY configuration consists of one Clock Lane and up to 4 Data Lanes. The number of Data Lanes is configurable. D-PHY is silicon proven with production level status in 65nm and 40nm nodes.

 

MIPI M-PHY Receiver IP core (HIPA 11100)

The MIPI Rx M-PHY is a high frequency, low power IP compliant with the MIPI Alliance Standard for M-PHY version 1.0. It can be used as Physical Layer for interfaces in the products such as camera, display, audio, video, power management and communication between BB (Base Band) and RFIC. It's used to receive and recover the embedded clock and data on Rx differential lane. The MIPI Rx M-PHY support two modes of data reception: HS (High Speed) and PWM LS (Pulse Width Modulation Low Speed). Power efficiency throughput is ensured by using burst mode. Supports both optical and electrical interfaces and multiple power saving modes. M-PHY is silicon proven with production level status in 65nm and 40nm nodes.

 

MIPI M-PHY Transmitter IP core (HIPA 11000)

The MIPI M-PHY TRANSMITTER IP Core is a high frequency, low power IP compliant with the MIPI Alliance Standard for M-PHY version 1.0. It can be used as Physical Layer for interfaces in the products such as camera, display, audio, video, power management and communication between BB (Base Band) and RFIC. It's used to transmit data and clock on to the differential Tx lane. The high frequency clock is generated by the Tx PLL. The MIPI Tx M-PHY support two modes of data transmission: HS (High Speed) and PWM LS (Pulse Width Modulation Low Speed). D-PHY is silicon proven with production level status in 65nm and 40nm nodes.

 

MIPI UniPro IP core (HIP 3600)

HDL DH UniPro IP core (HIP3600) complies with the UniPro specification version 1.4. HIP3600 implements the Physical-Adapter Layer (L.15), Data Link Layer (L2), Network Layer (L3) and Transport Layer (L4) as well as support the M-PHY Layer of the standard. HIP3600 exhibits a complete set of component with bus-master and slave interfaces using AMBA AHB and AXI Version 2.0.

HDL Design House Product Press Releases

HDL Design House Introduces MIPI CSI-2 Transmitter IP core

 

 

Belgrade, Serbia – December 7th, 2012 - HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, today announced availability of MIPI CSI-2 Transmitter (HIP 3900), digital core that is compliant with the MIPI Alliance CSI-2 Specification, as part of HDL Design House FlexIP core library. CSI-2 (Camera Serial Interface) transmitter IP core (HIP 3900) is highly configurable, synthesizable digital IP core which receives pixels from camera sensor, performs packing in form of CSI-2 long packets and short packets, and sends them via PPI interface to the Host processor. HDL Design House CSI-2 Tx IP core can be combined with CSI-2 Rx and D-PHY IP cores, also available from the FlexIP core library, thus providing a complete, single-vendor MIPI CSI-2 solution.

 

HIP 3900 is compliant with the following specifications: CSI-2 (Camera Serial Interface) version 1.01, D-PHY version 1.0, AMBA3 AHB-Lite Protocol Specification version 1.0. The AHB interface is used for configuration of CSI-2 transmitter IP core, allowing external access to the core's 32-bit configuration, status, power management, and interrupt registers. The PPI interface is used to transmit pixel and command from external D-PHY, using independent High Speed (HS) and Low Power (LP) TX data paths. When in LP mode, the CSI-2 Transmitter IP core is used for Ultra Low Power control. In HS mode, the data is received using between 1 and 4 data lanes. Camera Pixel Interface is used to directly connect Camera sensor with CSI-2 Transmitter IP Core. HIP 3900 is a configurable IP core with more than 30 configuration and interrupt registers.

 

HDL Design House CSI-2 Transmitter IP core (HIP 3900) supports up to 4 data lanes, one clock lane and up to 4 virtual channels. HIP 3900 supports High Speed, Low Power and Ultra Low Power modes. It supports various pixel formats defined in CSI protocol version 1.01: YUV420 8-bit, YUV420 8-bit (legacy), YUV420 10-bit, YUV422 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit (CSPS), YUV422 8-bit, YUV422 10-bit, RGB888, RGB666, RGB565, RGB555, RGB444,RAW6, RAW7,RAW8, RAW10, RAW12, RAW14.

 

HDL Design House MIPI CSI-2 Transmitter IP core is available now, along with CSI-2 Rx and the silicon-proven MIPI D-PHY IP core in 65nm and 40nm.

 

HDL Design House has been a MIPI Alliance Contributor Member since 2010.

 

About HDL DH FlexIP core library

The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (M-PHY, D-PHY, DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html

 

About HDL Design House

HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006/2009. For more information, please visit www.hdl-dh.com

 

HDL Design House Announces MIPI DSI (Controller + D-PHY) IP Solutions

 

 

 

Belgrade, Serbia – November 26th, 2012 - HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, has announced availability of MIPI DSI Host (HIP 3500) and Peripheral (HIP 3510) IP cores, fully compliant with the MIPI Alliance DSI specification, as part of HDL Design House FlexIP core library. These DSI IP solutions can be used in tandem with HDL Design House MIPI D-PHY IP core, available in advanced technology nodes and with silicon proven status. HDL Design House has been a MIPI Alliance Contributor Member since 2010.

 

HDL Design House MIPI DSI Host IP core (HIP 3500) is a configurable digital core, compliant with the MIPI Alliance DSI specification, providing a high-speed serial interface between an application processor and MIPI DSI compliant display. It supports MIPI DSI protocol version 1.1, MIPI DCS version 1.0, MIPI DBI version 2.0, MIPI DPI version 2.0, MIPI D-PHY version 1.0. The HIP 3500 is fully compliant with AMBA AHB Version 2.0 Compliant Slave Interface. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits (a.k.a. RGB565, RGB666, RGB888).
 

HDL Design House MIPI DSI Periph (Device) IP core (HIP 3510) receives pixel data and commands from host processor through D-PHY interface and sends data to DPI or DBI interfaces. HIP 3510 is a highly configurable digital IP core, supporting 1 to 4 data lanes. The HIP 3510 is fully compliant to MIPI Alliance's DSI, MIPI DBI version 2.0, DPI version 2.0, and DCS standards, as well as to AMBA's AHB specification. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits, (a.k.a. RGB565, RGB666, RGB888). It supports both command and video modes of operation.

 

HDL Design House MIPI DSI solutions are available now, along with the silicon-proven MIPI D-PHY IP core in 65nm and 40nm.

 

About HDL DH FlexIP core library

The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (M-PHY, D-PHY, DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html

 

About HDL Design House

HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006/2009. For more information, please visit www.hdl-dh.com

 

 

HDL Design House MIPI M-PHY and D-PHY Solutions available in 40nm and 65nm

 

 

Belgrade, Serbia – December 18th, 2012 - HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, today announced availability of MIPI M-PHY and D-PHY solutions in advanced technology nodes. MIPI M-PHY and D-PHY solutions are fully compliant with the MIPI Alliance M-PHY and D-PHY specifications version 1.0, as the latest addition to HDL Design House FlexIP core library. These IP solutions can be combined with HDL Design House MIPI DSI and CSI-2 IP cores. As a MIPI Alliance Contributor member since 2010, HDL Design House offers high quality, silicon proven M-PHY and D-PHY solutions, available in 40nm and 60nm.

 

HDL Design House MIPI D-PHY is a high speed serial interface used for communication between components inside a mobile device. MIPI D-PHY can be used for point-to-point serial communications in high speed links like serial display interfaces (DSI), serial camera interfaces (CSI) and MIPI UniPro based module. The D-PHY Link includes a high speed signaling mode for both fast data traffic and low power signaling mode for control signal purposes. The D-PHY configuration consists of one Clock Lane and up to 4 Data Lanes, and the number of Data Lanes is configurable. Each Lane consists of an analog front end to generate electrical levels, detects signals from interconnects and translates them into digital values and control and interface logic to control I/O functions. It supports PPI (PHY Protocol Interface), and bandwidth ranges from 800 Mbps to 1 Gbps per lane depending on the process node.

 

HDL Design House MIPI M-PHY is a high frequency, low power IP compliant with the MIPI Alliance Standard for

M-PHY version 1.0. It can be used as Physical Layer for interfaces such as camera, display, audio, video, power management and communication between BB (Base Band) and RFIC. MIPI M-PHY supports two modes: HS (High Speed) and PWM LS (Pulse Width Modulation Low Speed), and power efficiency throughput is ensured by using burst mode. It supports both optical and electrical interfaces and multiple power saving modes. HDL Design House MIPI M-PHY can ensure data rates from 10Mbps up to 6Gbps.

 

HDL Design House D-PHY IP core can be used in tandem with MIPI DSI and CSI IP cores. HDL Design House MIPI M-PHY IP core can be combined with UniPro, LLI and DigRF digital controllers, also available from HDL Design House FlexIP core library.

 

About HDL DH FlexIP core library

The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (M-PHY, D-PHY, DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html

 

About HDL Design House

HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006/2009. For more information, please visit www.hdl-dh.com

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Standard products: Yes
Custom products: Yes

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