Mixel, Inc.

Member since 2006

Mixel® is a leading provider of silicon-proven, mixed-signal IP cores. Mixel licenses high-performance interface and timing IP, such as PHYs, SerDes, PLLs, and DLLs with a special focus on MIPI® cores. Mixel is pioneering a “legorithmic” approach, resulting in optimized and reusable IP implementation. Mixel’s best-in-class MIPI PHY cores, such as the D-PHY and M-PHY® address all of MIPI use models, including DSI, CSI, UniproSM, and DigRFSM, as well as emerging JEDEC use models such as UFS.

Mixel was founded in 1998, and is based in San Jose, CA, USA. Mixel is at the forefront of contributing to a vibrant MIPI ecosystem, by working closely with other stakeholders such as digital IP providers, verification IP providers, and instrumentation companies to help accelerate MIPI adoption.

Learn more about Mixel, Inc. at www.mixel.com

Request information: info@mixel.com

See our demo videos: http://www.youtube.com/user/MixelInc
 

Mixel, Inc. Product Information

MXL-M-PHY: 
The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance specification for M-PHY. The IP can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, power management and Baseband to RFIC.

It is compatible with all MIPI use-cases such as CSI-3, DSI-2, DigRF v4, Unipro 1.6 and Universal Flash Storage (UFS) specification. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates. The core employs Mixel’s Logarithmic approach, enabling efficient implementation of multiple configurations.

MXL-M-PHY-DigRF:
The MXL-M-PHY-DIGRF is a compliant with the MIPI Alliance specifications for M-PHY and DigRF v4. The IP can be used as a physical layer  on both Baseband and RFIC interface. It supports the DigRF v4 specification.

MXL-D-PHY-UNIVERSAL:
The MXL-PHY-MIPI-UNIVERSAL is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance  D-PHY specification. The IP can be configured as a MIPI master or slave and consists of 5 lanes: 1 Clock lane and 4 data lanes.

The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.

MXL-PHY-CSI2-RX: The MXL-PHY-CSI2-RX is a Physical Layer compliant with the MIPI Alliance  D-PHY Specification. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI2).

MXL-PHY-CSI2-TX: The MXL-PHY-CSI2-TX is a Physical Layer compliant with the MIPI Alliance  D-PHY Specification. The IP is configured as a MIPI master and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for camera interface applications (CSI2).

MXL-PHY-DSI-RX: The MXL-PHY-DSI-RX is a Physical Layer compliant with the MIPI Alliance  D-PHY Specification. The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display interface applications (DSI).

MXL-PHY-DSI-TX: The MXL-PHY-DSI-TX is a Physical Layer compliant with the MIPI Alliance  D-PHY Specification. The IP is configured as a MIPI master and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display interface applications (DSI).

MXL-PLL-MIPI: The MXL-PLL-MIPI is a high performance PLL based frequency synthesizer. It is highly integrated and requires no external components. Differential circuit techniques are employed to attain low jitter in the noisy environment typical of multi-million gates digital chip. The IP is optimized for integration with Mixel D-PHY IP.

MXL-PLL-MIPI-PXL: The MXL-PLL-MIPI is optimized for use with MIPI MIPI D-PHY IP for generating the high frequency clock needed for the D-PHY data transmission and the pixel clock required in a typical MIPI system. The IP supports a unique low power mode, where a by-2 multiplier generates an output clock while the PLL is powered down.

MXL-MIPI-LVDS-BRDG: The MXL-MIPI-LVDS-BRDG is a MIPI/LVDS bridge IP compliant with the MIPI Alliance Specification for D-PHY on both the TX and RX sides. Additionally it supports three other specifications on the RX side, namely SMIA, HiSPi (SLVS) and HiSPi (HiVCM). The IP incorporates 5 lanes each operating at speeds up to 1.2Gbps.

Learn more about Mixel, Inc.

Learn More about Mixel, Inc. Products

Mixel, Inc. Product Press Releases

1.       GEO Deploys Mixel MIPI solution in its Geometric Processing IC for Ultra-Wide Angle Cameras

2.       Kawasaki Microelectronics Achieves First-Silicon Success with Mixel’s MIPI and MIPI/LVDS Unified Solutions

3.       Mixel and Graphin Demonstrate World’s First End-to-end Video Transmission Using M-PHY Link

4.       ECT’s World’s first 3D chip supporting MIPI employs five Mixel MIPI products

5.       Mixel Achieves First Silicon Success with its MIPI M-PHY IP

6.       Mixel Spearheads a MIPI Alliance Ecosystem Partnership

7.       Mixel and Northwest Logic Deliver a Unified MIPI Platform Supporting both CSI-2 and DSI

8.       ROHM First to market with Mixel’s Unified MIPI/MDDI PHY IP solution in its Mobile Display Driver Chip

9.       Mixel’s MIPI D-PHY IP Licensed by Canesta

10.   Mixel and Graphin Announce a MIPI M-PHY Strategic Partnership

11.   Mixel first to market with Unified MIPI/MDDI PHY IP solution

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