Synopsys, Inc

Member since 2006

Specific Division(s): Solutions Group

Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.  

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Synopsys, Inc Product Information

DesignWare MIPI DigRF v4 Master Controller IP:

 

Synopsys’ DesignWare® MIPI DigRF v4 Master Controller IP is compliant to the MIPI Alliance DigRF v4 specification. The DigRF v4 specification defines a high-speed, serial, digital chip-to-chip interface and communication protocol that connects baseband processor ICs and RF ICs. The DesignWare MIPI DigRF v4 Master Controller IP is fully configurable to enable support for up to 4 receive (RX) channels and 4 transmit (TX) channels, and can be used for basic handset configurations as well as with local and remote diversity. The DesignWare MIPI DigRF v3 Master Controller IP is ideal for mobile terminals that support high-bandwidth mobile broadband standards, such as LTE and Mobile WiMax.

 

DesignWare MIPI M-PHY IP:

Synopsys’ DesignWare® MIPI M-PHY IP is compliant to the MIPI® Alliance M-PHY specification and supports a wide range of advanced CMOS digital logic processes. The fully integrated M-PHY hard macro is a high-speed serial interface to the DigRF v4 and UniPro interconnect standards of the MIPI Alliance. The high-quality DesignWare MIPI M-PHY IP is designed to provide mobile devices targeting 4G speeds with high data rates, low power consumption, effective power management schemes, robustness against RF interferences and low RF emission.

 

DesignWare MIPI DigRF v3 PHY IP:

Synopsys’ DesignWare DigRF v3 PHY IP is compliant to the MIPI® Alliance DigRF v3 specification and supports a wide range of advanced CMOS digital logic processes. The DigRF v3 PHY hard macro is a high-speed end-to-end bidirectional serial link using a single interface for transferring data and control information between digital baseband processors and RF ICs in single or dual-mode 2.5G/3G applications. The DigRF 2.5G-3G PHY implements the physical layer of the MIPI Alliance DigRF v3 interface and implements all the functionalities needed for clock multiplication, low power and test modes.

 

DesignWare MIPI DigRF v3 Master Controller IP:

 

The Synopsys DesignWare MIPI DigRF v3 Master Controller IP is a configurable core that is compliant to the MIPI® Alliance DigRF v3 interface specification which defines a chip-to-chip communication protocol between the digital BaseBand IC and the Analog Baseband/RF IC, for 3GPP 3G/2.5G (UMTS/EGPRS) mobile terminals.

 

The DesignWare MIPI DigRF v3 Master Controller IP core in conjunction with the Synopsys DesignWare DigRF v3 PHY provides a comprehensive solution to design a Digital Baseband IC for communicating with a DigRF-compliant Analog Baseband RFIC. The DesignWare MIPI DigRF v3 Controller is integrated with the physical layer through simple serial interfaces for both transmit and receive channels. The DesignWare MIPI DigRF v4 Master Controller IP uses an AMBA-APB slave port for configuration of DigRF Physical Layer parameters and transmitting commands over the DigRF interface.

 

DesignWare MIPI DigRF v3 Slave Controller IP:

The Synopsys DesignWare® DigRF v3 Slave Controller IP implements the protocol layer of the MIPI Alliance DigRF v3 Interface Specification, bringing DigRF connectivity into the RF Transceiver (RF IC) for communication with DigRF-compliant digital baseband processors. The DigRF v3 specification defines a bidirectional serial link which uses a single interface for transferring data and control information between digital baseband processors and RF Transceivers in single or dual-mode 2.5G/3G applications. The DigRF interface also conveys control / status information to / from the RF Transceiver.  All interface control functions are implemented by the DigRF protocol layer based on the control frames received through the Physical interface.

 

The DesignWare MIPI DigRF v3 Slave Controller is designed to interface with the Synopsys DesignWare DigRF v3 Physical layer, based on simple 3-wire serial interfaces for data transfer.

 

DesignWare MIPI DSI Host IP:

The Synopsys’ DesignWare®MIPI DSIHost Controller IP is a configurable digital core that is compliant with theMIPI® Alliance DSIspecification, providing a high-speed serial interface between a application processor and MIPI DSI compliant camera display. The DesignWare MIPI DSI Host Controller is fully compliant to the Display Serial Interface (DSI), the Display Pixel Interface (DPI-2), and the Display Bus Interface (DBI-2). The DesignWare MIPI DSI Controller supports all commands defined in the MIPI Alliance Display Command Set (DCS) and interfaces with D-PHYs that support the PHY Protocol Interface (PPI). The DesignWare MIPI DSI Host Controller IP can be configured to handle 1 to 4 data lanes and can support display resolutions from 160x120 (QQVGA) to 1024x768 (XVGA). The DesignWare MIPI DSI Host Controller supports video mode pixel formats for 16 bpp(5,6,5 RGB), 18 bpp(6,6,6,RGB) packed, 18 bpp(6,6,6,RGB) loosely, and 24 bpp(8,8,8,RGB) and has ECC and Checksum capabilities;

 

The DesignWare DSI Host Controller IP is architected to interface with the physical layer through the MIPI recommended PPI, providing easy integration to a D-PHY such as the highly optimized Synopsys DesignWare D-PHY IP.

 

DesignWare MIPI CSI-2 Host IP:

The Synopsys’ DesignWare MIPI CSI-2 Host Controller IP is a configurable digital core that is compliant with the MIPI Alliance CSI-2 Specification, providing a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.

 

The DesignWare MIPI CSI-2 Host Controller IP can be configured to handle 1 to 4 data lanes and support data transfers from 80 Mbps in Low-Power mode to 1 Gbps per lane in High-Speed mode for a total throughput up to 4 Gbps. The DesignWare MIPI CSI-2 Host Controller handles all packet decoding and all CSI-2 specified data formats. The core also handles complete error detection and correction at the PHY level through the PHY Protocol Interface (PPI), packet, line and frame level, thus ensuring reliable high-speed data transfer.

 

The Synopsys DesignWare MIPI CSI-2 Host Controller IP is architected to interface with the physical layer through the MIPI recommended PPI, providing easy integration to a D-PHY such as the highly optimized Synopsys DesignWare D-PHY Slave IP. The DesignWare MIPI CSI-2 Host Controller includes an AMBA APB interface for configuration, control and access to of the CSI-2 IP’s register bank.

 

DesignWare MIPI Bidirectional D-PHY IP:

The Synopsys DesignWare® MIPI Bidirectional D-PHY IP is an integrated hard macro which can be implemented with bidirectional lanes and optimized for the MIPI CSI-2, DSI or UniPro interfaces. The DesignWare MIPI D-PHY can be configured as both a Master and Slave D-PHY and is compliant to the latest MIPI D-PHY specification. The DesignWare MIPI D-PHY IP includes all the analog and digital circuitry and supports multiple low power modes including shut down and multiple test modes for increased reliability. The DesignWare MIPI D-PHY IP implements the MIPI recommended PHY Peripheral Interface (PPI) to ensure ease of integration with the protocol controller layer. The DesignWare MIPI D-PHY provides a high-reliability, high-speed differential interface minimizing the number of signals while reducing overall EMI.

 

DesignWare MIPI Slave D-PHY IP:

The Synopsys DesignWare® MIPI Slave D-PHY IP is a fully integrated hard macro which can be implemented and optimized to work with the MIPI CSI-2 or DSI interfaces. The DesignWare MIPI D-PHY is a Slave D-PHY and is designed to conform to the latest MIPI D-PHY specification. The DesignWare MIPI D-PHY IP includes all the analog and digital circuitry and supports multiple low power modes including shut down and provides multiple test modes for increased reliability. The DesignWare MIPI Slave D-PHY IP implements the MIPI recommended PHY Peripheral Interface (PPI) to ensure ease of integration with the protocol controller layer. The DesignWare MIPI Slave D-PHY provides a high-reliability, high-speed differential interface minimizing the number of signals while reducing overall EMI. The DesignWare MIPI Slave D-PHY IP is an ideal solution for MIPI CSI-2 and DSI interfaces.

 

  

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Synopsys, Inc Product Press Releases

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