MIPI CSI-2 and MIPI CSI-3 are the successors of the original MIPI camera interface standard, and both standards continue to evolve. Both are highly capable architectures that give designers, manufacturers – and ultimately consumers – more options and greater value while maintaining the advantages of standard interfaces.
The bandwidths of today’s host processor-to-camera sensor interfaces are being pushed to their limits by the demand for higher image resolution, greater color depth and faster frame rates. But more bandwidth is simply not enough for designers with performance targets that span multiple product generations.
The mobile industry needs a standard, robust, scalable, low-power, high-speed, cost-effective camera interface that supports a wide range of imaging solutions for mobile devices.
The MIPI® Alliance Camera Working Group has created a clear design path that is sufficiently flexible to resolve not just today’s bandwidth challenge but “features and functionality” challenges of an industry that manufactures more than a billion handsets each year for a wide spectrum of users, applications and cost points.
Additional details are available in the MIPI Camera CSI-2 Specification Brief.
The latest Camera Serial Interface 2 Specification (CSI-2 v1.3) offers higher interface bandwidth and greater channel layout flexibility than its predecessor. It introduces C-PHYSM 1.0, a new PHY that MIPI Alliance released in September 2014, as well as support D-PHYSM 1.2 interface.
Both PHY options improve skew tolerance and provide higher data rates. Both are serial interfaces that address many of the problems of parallel interfaces, which consume relatively large amounts of power, are difficult to expand and can be proprietary.
Using D-PHY maintains compatibility with earlier versions of the specification and lets vendors leverage their existing product development infrastructure. C-PHY requires a minimum of three control pins instead of six four and does not offer provides pin-wise backwards compatibility with D-PHY. Designers can implement standalone C-PHY, D-PHY or combo C/D-, however, mix and match the two PHY options to ensure longer-term design viability.
The CSI-2 protocol contains transport and application layers and natively supports C-PHY, D-PHY, or combo C/D-PHY. The camera control interface for both physical layer options is bi-directional and compatible with the I2C standard.
The CSI-2 Specification defines standard data transmission and control interfaces between the camera as a peripheral device and a host processor, which is typically a baseband, application engine.
D-PHY as used in CSI-2 is a unidirectional differential interface with one 2-wire forwarded clock lane and one or more 2-wire data lanes. The updated D-PHY specification, v1.2, introduces lane-based data skew control in the receiver to achieve a peak transmission rate of 2.5 Gbps/lane or 10 Gbps over 4 lanes, compared to the v1.1 peak transmission rate of 1.5 Gbps/lane or 6 Gbps over 4 lanes.
C-PHY consists of one or more unidirectional 3-wire serial data lanes or “trios”, each with its own embedded clock. MIPI C-PHY uses 3-phase symbol encoding of about 2.28 bits per symbol on a trio where each trio operating at 2.5 Gsym/s provides an equivalent of 5.7 Gbps per lane. Three trios operating at the C-PHY v1.0 rate of 2.5 Gsym/s provides 17.1 Gbps over a 9-wire interface.
CSI-2 over C/D-PHY imaging interface does not limit the number of lanes per link. Transmission rate linearly scales with the number of lanes for both C-PHY and D-PHY. The Figure below illustrates the connections between a CSI-2 Image Sensor transmitter and an Application Processor receiver using 6-pin C/D-PHYs, which are typically used on Mobile Platforms.
The OIS (Optical Image Stabilizer) and AF (Autofocus) are typically included with the Image Sensor as part of the camera module. The Gyro and Flash used for imaging may reside elsewhere on the platform.
The figure below illustrates the benefits of CSI-2 logical port configurations with embedded clock and data. A myriad of imaging use cases can be mapped on multiple port configurations. Embedded clock and data (CD) lanes provide configurable logical port realizations on CSI-2 platforms.
The figure above illustrates the basic configuration of a CSI-3 v1.1 system over 6 pins using maximum channel rate of 5.8 Gbps per lane. CSI-3 v1.1 supports high-resolution and high-frame-rate sensors, digital still cameras, video recorders and camera arrays. Products implementing CSI-3 v1.1 can transmit a 12 BPP, 30 FPS 4K video using a single data lane for pixel data and one slower backward lane for configuration and control.
By employing a packet-based transmission scheme, CSI-3 v1.1 enables subsystem architectures without line buffers. Message interleaving, in-band control and integration into network architectures are other features enabled by packet-based communications. Up to 32 virtual communication channels can be configured with support for in-band interrupts and control to respond quickly to demanding camera control requirements. Notification channels have been reserved for metadata such as, PDAF information, error conditions, status information, and for multimedia data. Optical interconnects are supported in the physical to address EMI issues arising from metal interconnects.
Within a camera subsystem, various components such as a RAW camera sensor, an SOC camera, a multichip camera module or an ISP can be connected to each other using a proprietary interconnect.
The number of lanes carrying data from the camera to the host is scalable from 1 to 4, allowing to achieve usable effective bandwidth of 17.8Gb/s. The back-channel (Host to Camera) consists of one lane and it can be typically configured to transmit with 1Gb/s, thus allowing a command latency of <1μs, and a transfer of 4KB of configuration data in less than 4μs.