Low Latency Interface Specification


Low Latency Interface Specification

In May 2014, the LLI WG released the latest version of MIPI Alliance Specification for Low Latency Interface v2.1. Click here to view the spec brief.

Specifications are available to MIPI members only. For more information on joining MIPI, please go to Join MIPIspecifications are available to MIPI members only. For more information on joining MIPI, please go to Join MIPI.

Architectural Overview

The Low Latency Interface (LLI) is a point-to-point interconnect that allows two devices on separate chips to communicate as if a device attached to the remote chip is resident on the local chip. The connection between devices is at their respective interconnect level, e.g. OCP, AMBA® protocols, using memory mapped transactions. A LLI Link is a bidirectional interface allowing either device to initiate transactions.

LLI primarily targets low-latency cache refill transactions. The low latency use cases are supported by the dedicated Low Latency traffic class (LL TC). The LLI specification is expressed as a layered, transaction level protocol, where Targets and Initiators on two linked chips exchange Transactions without software intervention. Software is used only to configure the LLI Link, for error handling and potentially, to initialize the LLI Stack. This configuration reduces latency and allows software compatibility regardless of the partitioning of the hardware on the two linked chips

In order to increase LLI’s utility, a best effort traffic class is also defined that allows access to memory mapped remote devices without decreasing the performance of any low-latency traffic.

LLI also provides a special set of Transactions for transmitting sideband signals between two chips connected with a LLI Link. Semantics of these sideband signals are not specified and can be used for any purpose. This feature can reduce the pin count on both chip packages.


The specification defines the protocol used to transfer data between Devices. This definition includes descriptions of data structures used to convey information across the interconnect. In addition, flow control, power management, and connection services are also within the scope of this document.

Translations of hardware interconnect transactions to LLI transactions, mobile terminal architectures, and protocol stack implementations are out of scope. 


This specification can be used by design engineers and architects to develop products that require a low latency interface between two devices. In addition, test and conformance engineers can use this specification to develop test plans to verify product implementations meet design goals.


Note: This is a typical LLI environment. It is only illustrative and does not represent all possible LLI implementations.

LLI_Spec_Brief_2014_FINAL.pdf124.9 KB