Working Groups: Overview
 Battery Interface Working Group
The Battery Interface (BIF) Working Group was established in March 2010 to define a robust, cost-efficient communication interface specification for smart batteries and low cost batteries. The BIF WG will investigate a low-speed, single-wire interface for communication between the mobile terminal and battery pack.
The fundamental requirement for a battery interface is to provide a method to communicate enough information to ensure safe and efficient charging in any environmental conditions. While low cost battery interface supports battery chemistry and capacity detection for basic safety, a smart battery interface with security features can offer strong protection against use of counterfeit batteries, providing a safer solution for mobile terminal end users.
Battery chemistries are evolving rapidly and will present new challenges to charge control, battery life time prediction and other similar subjects. The BIF WG will consider future expandability and room for user-defined, innovative functions and services for differentiation. The BIF WG reviews other standards in the mobile battery technology area to comply with relevant parts of them.
In terms of the OSI reference model, the BIF specification will consist of Data Link Layer and Physical Layer definition. The BIF WG considers existing proven solutions when possible.
Camera Working Group
The Camera Working Group was formed by the MIPI® Board of Directors to enable industry convergence onto a robust, scalable, power efficient serial interface for imaging peripherals and host processors. As MIPI gathered initial early momentum in 2004, CWG group initially forwarded the legacy MIPI Camera Serial Interface 1.0 specification for approval and began efforts on the next generation.
During 2004-2005, strong participation from a diverse set of member companies produced a major revision to CSI the "Camera Serial Interface 2 v1.0" specification.
CSI-2 specifies the details of protocol transmission over the D-PHY physical layer, a separate specification from the MIPI PHY Working Group. Its scope covers the transmission of serial data from a peripheral to a host processor, including packet formatting, data formats, and error detection and correction. CSI-2 v1 did not address detailed command and control issues, since they vary widely across implementations from different manufacturers and in different OEM software.
Currently, the Camera Working Group focuses on a next generation serial interface, which will expand CSI-2's scope to include some aspects of command and control, moving high bandwidth transmissions across the PHY Working Group's upcoming M-PHY physical layer using the UniPro Working Group's UniPro application layer.
DigRFSM
The DigRFSM WG was formed as a working group in April 2007. The group is focused on developing specifications for wireless mobile RFIC to BBIC interfaces in mobile devices.
The group's current charter is split into short and long term development efforts. The short term development will focus on a specification targeted for completion by end of 2007 for LTE and WiMax air interface standards. The longer term development will focus on future air interface standards which promise further improvements in high speed, data optimized traffic. In addition, the future work will seek to harmonize efforts with the PHY and UniPro Working Groups.
These specifications will describe the logical, electrical and timing characteristics of the digital RF-BB Interface with sufficient detail to allow physical implementation of the interface, and with sufficient rigor that implementations of the interface from different suppliers are fully compatible at the physical level.
Please read the following IMPORTANT NOTICE before selecting the link to view the DigRF BASEBAND/RF DIGITAL INTERFACE SPECIFICATION Version 1.12: IMPORTANT NOTICE
Display Working Group
The Display Working Group was formed to develop specifications for processor-to-display interconnect on handheld platforms. Such specifications should:
- meet all functional and reliability requirements using less power than existing solutions
- enable scalable high performance for higher-resolution LCD panels
- substantially reduce pincount compared to legacy parallel interfaces
- meet all requirements above at equivalent or lower cost compared to legacy parallel interfaces
- offer a market lifetime lasting through several generations of mobile display
The Display Working Group first developed and approved a pair of specs - DBI-2 and DPI-2 - that offer standardized and updated versions of "legacy" parallel interfaces for "Command Mode" and "Video Mode" architecture display panels, respectively. The WG then developed two new specifications, Display Serial Interface (DSI) and Display Command Set (DCS), which were approved by the MIPI Board in early 2006. DSI specifies a packet-based protocol layered above D-PHY, the MIPI physical-layer specification from the PHY Working Group. At the application level above DSI, DCS specifies an industry-standard command set for displays with on-panel controllers and frame buffers. In July 2006, DWG finished work on several updates and minor changes to DSI.
Press Release Announcing DSI Approval
High-Speed Synchronous Interface Working Group
MIPI High Speed Synchronous Interface (HSI) is one of the Legacy Specifications MIPI issued several months after its creation in 2003. The HSI 1.0 interface is widely used in a variety of products as a Baseband-Application processor link.
The HSI Working Group worked on enhancements of the Physical Layer in a new specification release, HSI Physical Layer v1.01. This new release provides improvements to the previous version of the HSI physical layer such as increased serial link efficiency, and potential pin-count reduction. In addition, this new physical layer no longer requires a specific protocol layer, and may implement proprietary protocols if desired.
Low Latency Interface Working Group
The Low Latency Interface (LLI) Working Group was established in March 2010 to define a Low Latency Interface enabling memory sharing between two devices. LLI is a bidirectional interface that transports memory transactions between two devices and allows a device to access the local memory of another device as if they were a single device.
LLI will support execution and boot from a remote memory. The transactions supported by LLI will establish a link between two remote interconnects (e.g. OCP, AMBAŽ protocols) without software intervention. LLI supports two physical links: M-PHYSM for chip-to-chip interfaces and CMOS I/O (TSV, DDR I/O) for die-to-die interfaces.
Low-Speed Multipoint Link Working Group
The charter for the Low-Speed Multipoint Link (LML) Working Group tasks the group to develop a very low pin count and low cost communications interface that has the potential to consolidate the numerous low speed audio and control interfaces found in today's portable handheld devices. Targeting replacement of I2C, SPI, microWire, and UART combined with various flavors of I2S, PCM, AC-97 and SPDIF audio interfaces on one link, the flexible boundary of control and isochronous data bandwidth can dynamically adapt to changing use cases.
The specification called Serial Low-power Inter-chip Media Bus (SLIMbus®), includes a two-wire, low voltage CMOS physical layer with a time division multiplexed link layer as a foundation for a set of messages and data channels. Messages are defined for bus and channel management, and are extensible into sets called Device Classes. Simple Device Classes are included for a host, clock generation (called a Framer), bus management (called the Interface), and a set of core messages necessary for future application-level Device Classes. SLIMbus will not address these application-level Device Classes in the initial version of the specification. The SLIMbus specification is available to MIPI members.
Press release announcing SLIMbus® specification
NAND Software Working Group
The NAND Software Working Group was established by the MIPI Alliance to investigate software interface standardization which may ease integration of NAND products into SW platforms. The group includes leading NAND flash memory manufacturers.
The Working Group will focus state-of-the-art software architectures comprising embedded NAND-like Flash storage management and anticipating NAND flash trends. The group intends to develop specifications standardizing the SW interfaces between the identified architecture components that would be under the responsibility of NAND flash manufacturer and produce complementary documentation to promote and aid the use of this interface.
The architecture and interfaces defined by the NAND SW Working Group target compatibility with existing and future operating system architectures.
Peripheral and interconnect Low-level Framework Working Group
The Peripheral and interconnect Low-level Framework (PLF) working group provides standardized services and software interfaces for users of MIPI peripheral devices within a MIPI system. These services allow for portability of software peripheral drivers and applications between systems, easing the task of integrating a new peripheral into a system. The services include a common means to access device identification and capability information over different MIPI Interfaces, and a complete software framework to support portable driver software.
The group supports definition of groups of devices (Device Classes) so that common software can manage devices within the class, yet still be able to retrieve device-specific information (such as the size of a display or gain adjustment parameters). Peripheral software can also operate independently of the MIPI Interface in use, allowing a greater variety of peripheral device implementations.
The workgroup is also a resource for other workgroups for software and service design issues.
The workgroup has several work items:
- DDB (Device Descriptor Block) specification for Levels 1 and 2 which describes services for accessing device information independently of the MIPI interface
- IMF (Interface Management Framework) specification which defines interfaces for use by portable peripheral drivers to access MIPI peripherals
- Device Class templates and processes
Physical Layer Working Group
The PHY Working Group is chartered to specify high-speed physical layer designs to support multiple application requirements. The first specification developed by the PHY WG was targeted primarily to support the requirements of camera and display applications. The resulting standard, D-PHY, is a low-power, differential signaling solution with a dedicated clock lane and one or more (scalable) data lanes. In addition to supporting MIPI CSI-2 and DSI standards, D-PHY will also support MIPI's emerging UniPro specification. To support longer term requirements for more advanced applications, the PHY WG has begun preliminary development of a higher speed, embedded clock design, called M-PHY.
RF Front-End Control Working Group
RF Front-End Control (RFFE) was established as a working group in October 2008. The scope is to define a control interface solution for RF front end modules and components. The distinction to DigRF is that whereas DigRF covers the RF IC - BB IC interface, RFFE will cover the control interface from the RF IC to the various front-end modules, i.e. power amplifiers, low noise amplifiers, filters, switches, DC/DC-converters and antennas.
The complexity of the RF front-end is increasing. More and more systems and frequency bands must be supported. Eventually the amount of control performed via dedicated control signals has reached such levels (tens of dedicated signals) that a control bus has become a desired solution.
A multitude of the front-end components currently and even in future will be based on relatively wide geometry silicon processes. A low complexity solution is essential with such prerequisites. Another key requirement is low EMI as the control solution will operate in a very EMI susceptible environment where tiny disturbances can destroy the RF performance and make the solution useless.
RFFE will look into existing simple control solutions (i.e. outcome from MIPI working groups LML and SPMI as well as other possible options) and re-use existing technology. Emphasis will be put on quest for simplicity and EMI robustness, both as source and victim. Signal paths in the RF front end are left out of the scope being currently analog signals. Co-operation with DigRF is needed since RFFE commands might be tunneled over DigRF in some RF control architectures.
Software Working Group
The Software WG is a group of software experts responsible for software-related activities within MIPI. This WG is actively collaborating with all MIPI working groups to ensure successful integration of the MIPI interface into software platforms and encourage compatibility between working groups in terms of software usage.
The Software WG is also active in the software sub-groups of other MIPI WGs and reviews proposals for new MIPI Working Groups which may develop software specifications related to MIPI Interfaces.
System Power Management Working Group
The System Power Management (SPM) Working Group is developing standard power control interfaces for mobile systems. These interfaces may impact both hardware and software domains. In the hardware domain, a System Power Management Interface (SPMI) specification is being developed for systems with multiple masters and slaves. The SPMI protocol replaces several existing buses to minimize component pin count. In the software domain, a standard software interface is being considered to enable operating systems and software applications to more effectively control the power state of hardware components or sub-modules in a system. A white paper is available which describes these interfaces within the context of a typical system.
SPM White Paper (.pdf)
Test & Debug Working Group
The MIPI Test & Debug Working Group was established to enable the best test and debug support in all stages of mobile chip and equipment development. The specifications target hardware and software interfaces between systems-on-a-chip (SoC) and tools supporting test and debug. Key objectives of these standards are enabling low cost solutions and improving interoperability of hardware and software. To WG cooperates with other industry and standardization bodies to ensure alignment with related standards and technologies.
UniPro Working Group
The MIPI Alliance Standard for UniPro (Unified Protocol) defines a layered protocol for interconnecting devices and components within mobile systems such as cellular telephones, handheld computers, digital cameras, etc. UniPro allows these devices and components to exchange data at high data rates, at low pin counts and at low energy per transferred bit. A suite of general-purpose features aims to make UniPro applicable for a wide range of component types ( e.g. application processors, coprocessors, modems, peripherals) and different types of data traffic (e.g., control messages, bulk data transfer, packetized streaming).
The UniPro WG is currently developing the UniPro 1 point-to-point specification as well as the PIE (Processor Interface Emulation) specifications. Future developments in the UniPro WG will target support for a network of devices, including UniPro 1 endpoints.
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