The PHY Working Group is chartered to specify high-speed physical layer designs to support multiple application requirements. The first specification developed by the PHY WG was targeted primarily to support the requirements of camera and display applications. The resulting standard, D-PHY, is a low-power, differential signaling solution with a dedicated clock lane and one or more (scalable) data lanes. To support longer term requirements for more advanced applications, the PHY WG has released and continues to develop higher speed, low-power, embedded clock designs. M-PHY® uses differential signaling (on two wires) and supports several industry specifications developed by MIPI as well as other partner organizations. C-PHY provides camera and display applications with 3 phase encoding on a three-wire interface.
Click here for more information on UniPort-M. — www.mipi.org/mphyunipro
The physical layer, or PHY, is the heart of any advanced, serial interconnect standard. Very different peripherals often share similar requirements at the PHY level. Recognizing this, MIPI® developed a single D-PHY specification as a re-usable physical layer solution upon which MIPI camera interfaces, display panel interfaces, and general-purpose high-speed/low-power interfaces could be based. This helped streamline the development of multiple standards in MIPI, but also benefits the companies implementing these interfaces in semiconductor products, since much of the PHY engineering investment can be re-used on subsequent designs.
MIPI D-PHY delivers up to 2.5 Gbps per lane via an advanced source-synchronous, differential SLVS design which is scalable to the number of lanes required by the application—data lanes can optionally operate bidirectionally as needed. It meets the demanding requirements of low-power, low-noise-generation, and high-noise immunity which mobile phone designs demand.
The PHY Working Group has successfully launched M-PHY v3.0, the next step in the multiple high-speed GEAR roadmap, with bandwidth speeds reaching ~5.8 Gigabits per second per lane. The group continues its work on M-PHY to increase high speed bandwidth.
MIPI M-PHY is a high-frequency, low-power physical layer defined by MIPI Alliance Specification for M-PHYSM. The M-PHY can be used as a physical layer for many applications, including interfaces for display, camera, audio, video, memory and storage, power management and communication between Baseband and RFIC. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
It currently supports the following MIPI Specifications: DigRF v4, CSI-3, UniPro, and LLI. By special agreement with JEDEC, JC-64.1 Universal Flash Storage (UFS) uses UniPort-M, the combination of the M-PHY physical layer and MIPI UniPro Specifications. On June 20th, 2012, MIPI and the USB 3.0 Promoter Group announced the availability of the SuperSpeed Inter-Chip (SSIC) specification. SSIC utilizes the MIPI M-PHY physical layer with the SuperSpeed USB protocol and software layers to achieve high speeds and low power.
The most recent design to join the MIPI physical layer roadmap, C-PHY uses 3 phase encoding on a unidirectional three-wire interface to camera and display applications. It does not require a separate clock lane and provides flexibility to assign individual lanes in any combination to any port on the application processor via software control. Due to similarities in basic electrical specifications, C-PHY and D-PHY can be implemented on the same device pins. 3-phase symbol encoding technology delivers approximately 2.28 bits per symbol over a three-wire group of conductors per lane. This enables higher data rates at a lower toggling frequency, further reducing power.
Henrik Icking, Intel
Andrew Baldman, MIPI Alliance
Raj Kumar Nagpal, Synopsys