The MIPI Alliance Board of Directors established the System Power Management (SPM) Investigation Group (IG) in 2004, and it became a full Working Group (WG) in 2005. The SPM Working Group was chartered to standardize a power management architecture framework with power use models and a power management control interface.
A System Power Management Architecture Framework white paper has been developed to discuss software power management interfaces and architectures to effectively manage the power state of complex heterogeneous processors, systems, and modules to provide a foundation for the definition of the SPMI hardware specification.
The System Power Management Interface (SPMI) is a high-speed, low-latency, bi-directional, two-wire serial bus suitable for real-time control of voltage and frequency scaled multi-core application processors and its power management of auxiliary components. SPMI obsoletes a number of legacy, custom point-to-point interfaces and provides a low pin count, high-speed control bus for up to 4 Master and 16 Slave Devices with command acknowledgement for additional protocol reliability supported in SPMI v2.0. SPMI enables interrupt driven control of the power management system with the ability for Master and Slave SPMI Devices to be powered off for additional system power savings.
Christopher Chun, Qualcomm Inc.