Embedded Clock Option in D-PHY v3.5 Further Expands Specification’s Appeal

The latest version, v3.5, of the MIPI D-PHY℠ specification introduces an optional embedded-clock mode while keeping its existing electrical levels and supported channels in place—a combination that boosts the popular interface's suitability for evolving high-performance, cost-optimized cameras and displays. The enhancements delivered in D-PHY v3.5, which was made available last year to MIPI members, significantly broaden the appeal of the specification, particularly with the ability of the embedded-clock option to reduce wire count and support emerging high-bandwidth applications with lower electromagnetic interference (EMI) limits.

Because of its simplicity, flexibility, performance and power efficiency, D-PHY already has broad adoption across mobile, where it can be found in smartphones and tablets; in industrial use cases, such as in drones, surveillance cameras and industrial robots; and even in some automotive applications.

The new embedded clock mode scheme in v3.5 uses a well-known 128B/132B data encoding and offers clock data recovery (CDR) to support two-wire, high-speed communication without the need for dedicated clock lanes. Forwarded clock remains an option in v3.5, so designers have the choice to use either or both clock modes in a system. The embedded and forwarded clock modes are similar in terms of electrical characteristics, channels, state machine and LP mode. Also important, the new version maintains backward compatibility with previous versions of the specification.

Opting to use the embedded-clock mode frees a lane of traffic that otherwise would be required to carry the forwarded-clock signal. This means that v3.5 boosts the effective throughput of a D-PHY link between an application processor and a megapixel camera, a high-resolution display or other sensors. Furthermore, the functionality to de-skew clock-to-lane timing does not apply to an embedded clock system. In these ways, the MIPI D-PHY Working Group is evolving the specification to meet the growing sensor requirements for higher bandwidth, and to potentially reduce the number of wires needed in a system design.

Electromagnetic compatibility (EMC) and control of spectral density also are improved in the embedded-clock option, a consideration designers may find advantageous for systems demanding stringent EMC performance.

This update of the specification also adds minor clarifications and replaces outdated terminology in the document with more inclusive language that also more accurately reflects the functions of technical devices.

The MIPI D-PHY Working Group seeks participation in the development of the next major update to the specification, currently envisioned as v4.0. The current D-PHY v3.5 supports high-speed communication up to 9 Gigabits per second (Gbps) per lane, and plans for v4.0 include an increase to 16 Gbps for embedded-clock mode. AC coupling also is planned as an addition to DC coupling currently supported. In addition, a conformance test suite (CTS) for v3.5 is being created to improve the interoperability of products that adopt D-PHY.