27 October

T2 MIPI Verification and Test

• 10:15 | (T2) MIPI High Speed Serial Technologies: Debug & Conformance Testing Challenges and Solutions (Tektronix)

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  Abstract: The three high-speed serial standards namely - MIPI D-PHY, MIPI M-PHY and MIPI C-PHY, although having similarities in terms of target segment and application use cases, do have wide contrasts with respect to electrical specifications. MIPI D-PHY is a forwarded clock system, MIPI M-PHY has maximum toggle rate of up to ~12Gbps and MIPI C-PHY is 3-level 3-wire signal. Inevitably, engineers will encounter varied issue/challenges while debugging or testing these designs. This presentation shall provide real world problems faced and the process of uncovering them early on using the test and measurement equipment & solutions. The solution could be in terms of measurement & analysis of signal characteristics, probing with fidelity and waveform generation with precision. In addition, this session shall highlight the test solutions you will need to support the upcoming revisions of these MIPI PHY specifications.

  Ramesh from the past 20+ is working on developing compliance measurements for various technology like HDMI, MHL, Ethernet and MIPI . He also contributes to Standards specifications and test methodologies of many high speed serial technologies. Apart from measurement development, he also involved in solving the customer issues relating to Test and measurement and also instrumental in developing the system level solution for Testing. He holds 5 US patents for various T & M functionalities/procedures.

  Parthasarathy, Chair of the MIPI Test Working group at MIPI Alliance, is a System Engineer for MIPI technology segment at Tektronix. He is involved for the past 9 years working on signal generation solutions for waveform generators & measurement solutions for real-time oscilloscopes. His current focus is on test solutions for MIPI High Speed PHY Technologies. He holds a US patent for a method to emulate crosstalk. Prior to joining Tektronix, Partha was involved with embedded device drivers for mobile platforms and has designed algorithms for wide range of DSP solutions.

  

   

• 10:45 | (T2) Using the Protocol To Simplify PHY Testing: A Practical Example with UniPro (BitifEye)

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  Abstract: BitifEye demonstrates how to enable Physical Layer testing with help from the Protocol Layer. In particular we focus on MIPI UniPro and UFS devices, which can be easily tested through the UniPro Test Mode. It allows in-band link configuration as well as frame and error counter retrieval, standardizing the test setup and removing the need for out-of-band connections to the DUT. This reduces setup and test time and provides the most complete and reliable solution to test the Physical Layer. Complementary to the presentation, our booth will feature a live demonstration of the solution, using a UFS 2.0 Device from SMI. 

  Victor Sanchez-Rico is the Project Manager for the MIPI test software at BitifEye, Keysight’s Solutions Partner for high speed interfaces. This Computer Science engineer is also a father of three and a sports cars aficionado. He will solve all your testing needs while proudly showing you pictures of his daughters on his MIPI-enabled smartphone.

   

  

   

• 11:15 | (T2) MIPI M-PHY Gear4 and its impact on UniPort/UFS (Teledyne LeCroy)

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  Abstract: This presentation will review the features of MIPI M-PHY Gear 4 and their impact and implementation within UniPort/UFS Protocol. Teledyne LeCroy will discuss how UniPort and UFS will implement the higher speeds of Gear 4 and introduce the changes between UniPort Version 1.61 and Version 1.80. We will also present the changes from UFS 2.1 to UFS 3.0 and changes that should be noted in the Protocol between host and device.

  Roy Chestnut is the Director of Technical Marketing for the Teledyne LeCroy Protocol Solutions Group. Roy has been with the Protocol Solutions Group for 16 years. Along with his responsibilities as Director of Technical Marketing, he also has principle responsibility for the Teledyne LeCroy PSG Mobile and DDR product lines. Roy has been a member of MIPI Alliance since 2008. He has over 30 years of experience supporting High Speed Serial Data and Networking Protocols. Roy has a BS degree in Business Administration-Information Systems Management from San Diego State University and over 35 years of experience supporting High Speed Serial Data and Networking Protocols.

   

  

   

   

• 11:45 | (T2) SPMI 1.0 Multi-master Verification (Qualcomm)

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  Abstract: In the fast-growing mobile industry, there is a constant need of reducing the sizes of mobile chips, which is accomplished by reducing the number of pin connections in a chipset. SPMI protocol plays a vital role in doing so, as it supports multi-master and multi-slave systems. It is generally used to send transactions between the processor and the PMICs. There are occasions where the processor is in sleep, but the inter-PMIC communication exists. This motivation has led to the requirement of multiple SPMI masters – one on the processor and other on the PMIC. Since, the processor and the PMICs exist as different chips, there is a challenge to verify the multiple masters. A system-level test bench is required where both the masters are instantiated. The major verification efforts lie in validating the scenarios like multiple masters waking up at the same time and trying to connect, second master trying to connect when one master is already present, multiple masters and slaves arbitrating with different priority levels, BOM (Bus Owner Master) transfer, disconnection of a master using TBO (Transfer Bus Operation) or during hard reset or during command parity error, noise injection during various phases of a transaction and recovery after it, watchdog timer expiry and internal reset in the slave when SPMI clock is stopped abruptly during a transaction. Our paper elaborates on the multi-master multi-slave test bench and how the verification challenges were handled and closed.

  Sanjeev Kumar has around 8+ years of industry experience in ASIC Design Verification and is working with Qualcomm as a Senior Lead Engineer. He has expertise in the verification of peripheral IPs (SPMI, PMIC Arbiter), Ethernet IPs (MAC, Port) and Point-of-Sale (PoS) IPs. He has extensively worked in constraint random verification using System Verilog and UVM-based verification environment. He has done B.E. from BITS-Pilani and his hobbies are traveling, playing cricket/badminton and watching movies/TV series.

  Purva Joshi has around 4+ years of industry experience in ASIC Design Verification and is working with Qualcomm as an Engineer. She has experience in IP as well as SOC verification. She has expertise in formal verification. She holds a B.E. degree and her hobbies are playing badminton, gardening, watching movies.

  Ritesh Jain has around 16+ years of experience and is working with Qualcomm as a Senior Staff Engineer/Manager. He has an extensive experience in IP/CPU/Multi processor/SOC verification. He champions in the field of low power verification and mixed signal verification. He is a pass out of BITS-Pilani and has hobby as Painting.

   

  

   

• 13:15 | (T2) Dynamic Reconfiguration of MIPI UniPort-M Compliance Host (Western Digital)

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  Abstract: Day by Day we are moving through the process of MIPI Globalization in Mobile Industry by converting all the available interfaces (like camera, IPC and storage)to MIPI UniPort M based interface. Based on this point, even though silicon vendors are ready with MIPI controllers (i.e. DUT’s) its taking huge time to develop Host Platform for Validation of DUT. From this observation am coming up with a Reconfigurable Host for all UniPort-M based peripherals like Chip 2 Chip (i.e. IPC), Camera (i.e. CSI-3), Storage (i.e. UFS).By using this platform we can switch the host protocol on the fly between IPC , CSI-3 and UFS. The major advantage of designing this kind of host platform was to reduce the HW resource development time and cost. We have to use Xilinx Zynq FPGA as the processing module for building Reconfigurable Host. User will always have 3 different options to switch between different host protocols.

  Sreekanth Varma Dantuluri has been a VLSI/FPGA Engineer at Western Digital since 2014. He received his master’s degree in VLSI from IIIT in 2008. He has been actively participating in MIPI discussion’s and working on MIPI-based solutions for the past 3 years. He is very energetic in debugging MIPI UniPro and MIPI M-PHY related issues.

   

  

   

• 13:45 | (T2) Next Generation MIPI Physical Layer Design and Evaluation Challenges (Keysight)

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  Abstract: MIPI has released new MIPI C-PHY, MIPI D-PHY and MIPI M-PHY specifications this year to address the next generation of the 5G mobile era to include VR (virtual reality), AR (augmented reality) and autonomous vehicle technology. Those new MIPI PHY specifications will bring new technology innovation that will also bring new challenges to design or evaluation engineering. In this session, we will look at the key changes in the specification and CTS (conformance test suite) and address the challenges to support the new PHY layer. 

  SK Choi is the Keysight Technologies Solution Expert and Product Manager for MIPI Alliance solutions. SK is currently a contributor to the MIPI PHY Working Group and member of the MIPI TSG (Technical Steering Group). He has completed 10 years working for Keysight. He has a bachelor’s degree in Electrical Engineering from Korea.

   

  

   

• 14:15 | (T2) Overcoming Inter-Symbol Interference with MIPI PHYs Using Training Sequences (Synopsys)

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  Abstract: Today mobile devices achieve new heights in data rates with every new device. Higher data rates lead to the problem of inter-symbol interference. To overcome this issue, designers can use equalization circuit at the receiver. Equalizer matches the impedance of transmission lines to reduce the inter-symbol interference. Most common equalizer used in digital communication is the adaptive equalizer, which uses training sequences to get the required coefficient settings. The latest MIPI PHY specifications (M-PHY, D-PHY and C-PHY) introduce training sequences for the equalizer settings to reduce inter-symbol interference: adapt sequence in M-PHY, alternate sequence in D-PHY and C-PHY. In addition, C-PHY uses preamble and user-define sequences. This paper describes various training sequences used in MIPI PHYs to reduce inter-symbol interference.

  Manoj Sharma Tanikella is working as Sr. R&D Engineer at Synopsys India Pvt. Ltd. Responsible for designing Verification IPs as part of Verification Group at Synopsys. He urrently is involved in verification IP development of JEDEC UFS and MIPI portfolios like MIPI M-PHY, MIPI D-PHY, MIPI C-PHY, MIPI CSI-2, MIPI DSI and MIPI UniPro.

  Amitkumar Shrichand Gound is working as Sr. R&D Engineer at Synopsys India Pvt. Ltd. Amit is responsible for designing Verification IPs as part of Verification Group at Synopsys. He currently is involved in verification IP development of MIPI portfolios like MIPI M-PHY, MIPI D-PHY, MIPI C-PHY, MIPI CSI-2, MIPI DSI and MIPI UniPro.