27 October

T5 MIPI Connectivity

• 15:15 | (T5) C-PHY/D-PHY Combo Implementation and Use Case (Qualcomm & Mixel)

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  Ashraf Takla is President and CEO of Mixel, Inc., which he founded in 1998. Before founding Mixel, he was Director of Mixed-Signal Design at Hitachi Micro Systems. Ashraf has 35 years of experience in analog and mixed signal design, and holds 5 patents.

  C.K Lee is a Director of SERDES PHY design at Qualcomm Technologies, Inc. He has worked for Samsung and Enhanced Memory Systems before joining Qualcomm. C.K. has 27 years of experience in analog & mixed signal design.

   

  

• 15:45 | (T5) C-PHY and How it Enables Next Generation Display and Camera Implementations (Introspect)

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  Abstract: As a sequel to our previous MIPI C-PHY introduction presentations, we start by briefly covering MIPI C-PHY basics and the latest enhancements in recent revisions of the specification. Subsequently, we delve into a description of innovations in the next generation MIPI CSI-2 and MIPI DSI-2 protocols that are made possible by quite elegant properties of the MIPI C-PHY encoding scheme and its associated MIPI Alliance specification innovations. For example, we illustrate concepts of low latency, expanded virtual channel and interleaving support for IoT applications, and compression schemes such as those used in 30-bit display implementations.

  Dr. Mohamed Hafed is the Chief Executive Officer of Introspect Technology, a leading manufacturer of innovative test and measurement products for high-speed digital applications. A passionate technology speaker, Dr. Hafed contributes to the MIPI Alliance working groups, and he actively participates in MIPI technology promotion activities worldwide.

   

  

   

• 16:15 | (T5) Enabling Higher Data Rates and Variety of Channels with MIPI D-PHY (Synopsys)

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  Abstract: MIPI D-PHY is the de-facto standard for camera and display connectivity using low-latency transitions between high-speed and low-power modes with high noise immunity and high jitter tolerance. This presentation briefly describes MIPI D-PHY’s flexibility, speed, power and cost benefits for cameras and displays in mobile applications. Today, automotive infotainment and advanced driver assistance systems (ADAS) such as image, radar and lidar are also taking advantage of MIPI D-PHY’s unique benefits to allow higher data transmission over longer channels. In addition, camera and display applications based on D-PHY are seeing adoption in applications beyond mobile, like consumer, computing and multimedia. This presentation illustrates common use cases, and details how MIPI D-PHY can operate at 2.5 Mbps over multiple lanes to enable higher performance. The presentation will also give a brief roadmap of the D-PHY specification.

  Raj Kumar Nagpal currently serves as a Senior Staff Engineer in the Synopsys, Inc, Noida, India. He has over 24 years of research and industrial experience in various fields, including Signal integrity, power integrity, High speed links, RF engineering and Product Validations. He currently serves as the Synopsys, Inc. representative in MIPI PHY Working Group while managing the following positions: Chair MIPI D-PHY Sub Group and Vice Chair MIPI PHY Working Group. Prior to joining ST Microelectronics in 2001, he held various R&D positions in several organizations, including Defence Research and Development Organization (DRDO), Central Electronics Limited, Sahibabad, UP, and Scientific Instrument Co. Ltd., Ghaziabad. Mr. Nagpal has also co-authored and published extensively in IEEE conferences.

   

  

   

   

• 16:45 | (T5) IO Aggregation/De-Aggregation in Mobile and Mobile Influenced Systems to Improve Routing Congestion (Lattice)

  Abstract: Over the years, a large variety of low-speed I/O interfaces have proliferated in various systems in order to provide critical functionality such as: system configuration, power management, system resets, debug, firmware updates & other low-speed data communications. For example, consider the highest volume mobile system (Ref: MIPI System Diagram) there are about a dozen low-speed interfaces. Typically, these interfaces include multiple instances I2C, SPI, UART, SPMI and 1-wire.

  As the bandwidth requirement is small, these wires carry disproportionately higher cost per bandwidth compared to higher speed interfaces, say, based on D-PHY and PCI-Express. As the mobile components are being adopted in emerging mobile-influenced applications like drones, AR/VR, and automotive, these slow-speed interfaces tend to add non-trivial system cost, especially, if these have to be extended over longer distances and/or through connectors or hinges.

  In this presentation, we will address how to aggregate multiple slower-speed interfaces over one or two wires by using ultra-low power and small size mobile FPGAs. We will show that one or two wires running at speeds up to 100Mbps can carry the traffic associated with many of these interfaces as well as various GPIOs. We will discuss the tradeoffs involved among multiple requirements which include bandwidth, latency, number and types of interfaces, SW drivers and platform support.

  Satwant Singh is the Senior Director of Strategic Planning at Lattice Semiconductor, where he is responsible for ecosystem involvement for new developments and Lattice’s product capabilities roadmaps. Singh serves as the Vice Chair of MIPI Alliance’s RIO Working Group, as well as for the MIPI Sensor Working Group focused on developing new I3C interface specification. Singh holds a master’s of science in Electrical Engineering from the University of Toronto and has more than 30 patents.

   

  

   

• 17:15 | (T5) Emulation of DUT using UniPro RMMI as a Standard Interface (Western Digital)

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  Abstract: By using RMMI interface as the standard Interface we can do 100% functional validation when compared with functional verification. By using this technique the dependency on physical layers can be by-passed during initial stages of RTL or FW development. The only challenge here is to develop simple hardware connecting parallel lines of Host to DUT for RMMI interface. This method can be used to run regression’s on Emulation platform which will corner all the DUT RTL and DUT FW issue’s prior to RTL/ROM code freeze. When we run this kind of Emulation platform parallel to Simulation environment it will be an added advantage in identifying critical/corner issue which cannot be covered in Verification flow sometimes. By the time Physical Layer (Analog Block) is stable for Integration we can make sure Digital Block is also ready for RTL freeze. Finally by implementing this idea we can see few bugs in advance.

  Sreekanth Varma Dantuluri has been a VLSI/FPGA Engineer at Western Digital since 2014. He received his master’s degree in VLSI from IIIT in 2008. He has been actively participating in MIPI discussion’s and working on MIPI-based solutions for the past 3 years. He is very energetic in debugging MIPI UniPro and MIPI M-PHY related issues.