No. Some CCCs are mandatory, whereas others are optional and a given I3C Device will either support them or not, depending upon the Device’s capabilities.
Unlike I²C, there is no natural way to ‘hang’ the I3C Bus. In I²C, clock stretching (where the Slave holds the clock low, stopping it from operating) often causes serious problems with no fix: there’s simply no way to get the Slave’s attention if it has hung the Bus. By contrast, in I3C only the Master drives the clock, and so the Slave performs all actions on SDA relative to that clock, thereby eliminating the normal causes of such hangs.
I3C Slaves are only allowed to drive the Bus under certain situations. Besides during a read, and when ACKing their own address, they may also drive after a START (but not Repeated START). After a START, the I3C Bus reverts back to open-drain pull-up resistor mode; thus, the Slave that drives a low value (logic 0) would win.
No. The I3C CCCs are always preceded by I3C Broadcast Address, 7’h7E. Since the I2C specification reserves address 7’h7E, no legacy I2C Slave will match the I3C Broadcast Address, and thus would not respond to the I3C commands. Likewise, the Dynamic Addresses assigned to I3C Devices would not overlap the I2C static addresses, so an I2C device would not respond to any I3C address (even if it could see it).
Not directly, for a couple of reasons:
- The I3C Bus works with push-pull modes (in addition to the open drain for some transfers), and
- Much higher speeds. Most such devices are quite limited in speed, because of the lag effect of changing states on SCL and SDA due to both series-resistance and assumptions about open-drain.
Long wire approaches are being evaluated for a future version of the I3C Specification.
The maximum wire length would be a function of speed, as all the reflections and Bus turnaround must complete within one cycle. Larger distances can be achieved at the lower speeds than at the higher ones. For example at 1 meter (between Master and Slave), the maximum effective speed is around 6 MHz for read, to allow for clock propagation time to Slave and SDA return time to Master.
The I3C Specification lists the maximum per-Device capacitance on SCL and SDA, but the goal is that most or all Devices will be well below that. Capacitance alone is not sufficient to determine maximum frequency on the I3C Bus (as with any Bus). It is important to consider maximum propagation length, effect of stubs, internal clock-to-data (tSCO) of the Slaves, as well as capacitive load.