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            1 min read

            MIPI Webinar: A Framework for Moving Debug to the Internet of Things (IoT)

            Picture of MIPI Alliance MIPI Alliance : 19 November 2014

            MIPI GbD IPS MIPI GbD USB

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            View the webinar »

            Webinar Overview

            The need for low-level, non-intrusive debug visibility has only increased as SoCs have become more complex.  Unfortunately, access to the interfaces that support these functions (JTAG, Trace pins, etc.) has become more limited, particularly in fielded systems. Debug must move past this reliance on dedicated interfaces into a paradigm where the debug functions can co-exist with other system functions on shared interfaces and networks.

            MIPI has been developing a family of specifications that address this problem. The Gigabit Debug Framework defines “networkable” protocols that provide the same debug access and trace capabilities provided by the dedicated HW interfaces and tooling. Network-specific specifications then provide the details of how to map these protocols to various functional networks like USB, TCP/IP, etc.

            MIPI Gigabit Debug is not intended to displace other debug frameworks that also leverage functional networks as transports. Gigabit Debug is optimized for simple HW implementation, with little or no SW or OS interaction within the debug target. As such, the user can have a near “bare metal” debug experience and utilize the same on-chip debug resources that previously required dedicated debug interfaces.

            This webinar outlines the MIPI Gigabit Debug Framework as it exists today and provide a glimpse into where it is going in the future.

            Who Should Attend

            Anyone interested in debug of complex SoCs or network based debug technologies would benefit from attending.  This includes SoC architects, system software developers, debug tools vendors, and application software developers.

            Presenter

            Gary Cooper has been developing and supporting advanced debug technologies for Texas Instruments since 1998.  His primary focus has been increasing debug visibility on large SoCs. 

            Gary has been a member of the MIPI Debug WG since 2005 and has chaired the WG since 2009. Prior to this, he developed digital test instrumentation for the Department of Defense.  He has a BS in Applied Mathematics from the University of Pittsburgh and a MES in Computer Engineering from Loyola University Maryland.