MIPI C-PHY™

General Info

MIPI C-PHY™ provides a high performance, power efficient physical layer interface with a minimized number of interconnect signals to connect embedded cameras and displays to application processors. It uses an efficient three-phase coding scheme with embedded clock to reduce lane counts as well as minimize electromagnetic emissions to protect sensitive RF receiver circuitry.

C-PHY provides a physical layer for the MIPI Camera Serial Interface 2 (MIPI CSI-2®) and MIPI Display Interface 2 (MIPI DSI-2™) ecosystems, enabling designers to scale their implementations to support a wide range of higher-resolution, high-frame-rate image sensors and displays, while keeping power consumption and electromagnetic emissions low. The specification can be used to connect low-, mid- and high-performance image sensors and display panels, supporting the latest, most advanced, camera and display use cases. C-PHY can be applied for many use cases and industry segments, including mobile, wearable technologies, IoT, drones, personal computers and automotive.

MIPI C-PHY interfaces can coexist on the same device pins as MIPI D-PHY™, enabling designers to develop dual-mode devices. Operating data rates for a link can be asymmetrical, which enables implementers to optimize the transfer rates to system needs and also enables link operation using only C-PHY’s high-speed signaling levels. Bi-directional and half-duplex operation are optional.

Capabilities

MIPI C-PHY is an embedded clock link that provides extreme flexibility to reallocate lanes within a link. It also offers low-latency transitions between high-speed and low-power modes.

MIPI C-PHY accomplishes this by departing from a conventional differential signaling technique on two-wire lanes and using three-phase symbol encoding to transmit data symbols on three-wire lanes, or “trios,” where each trio includes an embedded clock. The encoding scheme equates to approximately 2.28 bits/symbol when using C-PHY’s 6-wirestate mode and 3.556 bits/symbol when using 18-wirestate mode.

When operating in 6-wirestate mode the specification supports symbol rates up to 6 Gigasymbols per second (Gsps) , equivalent to 13.7 Gbps, over a standard channel; and when operating in 18-wirestate mode the specification supports symbol rates up to 5 Gigasymbols per second (Gsps), equivalent to 17.8 Gbps, again over a standard channel. Three trios operating at 6 Gsps (6-wirestate mode) and 5 Gsps (18-wirestate mode) achieve a peak data rate of about 41 Gbps and 53 Gbps over a nine-wire physical interface. A Continuous-Time Linear Equalizer (CTLE) on the receiver enables operation at higher symbol rates.

Performance Highlights

MIPI C-PHY (6-wirestate mode) includes a fast bus turnaround (BTA), as well as an alternate low power (ALP) feature, which enables a link operation using only C-PHY’s high-speed signaling levels. These features enable applications of not only mobile devices, but also IoT devices operating over several meters at high speed. Also, these features enable an optional in-band control mechanism supported by the MIPI CSI-2 v3.0 Unified Serial Link (USL).

Latest Release

The newest version of MIPI C-PHY, version 3.0, introduces support for a new multi-phase 18-state coding scheme, referred to as “C-PHY 18-wirestate mode” which provides a 3.556 bits per symbol coding factor. The new coding option, transports 32 bits over nine symbols (32b9s), and maintains MIPI C-PHY’s industry-leading low EMI and low power properties. For camera applications, C-PHY v3.0 enables the use of lower symbol rates or lane counts for existing use cases or higher symbol rates with current lane counts to support new use cases involving the next generation of image sensor.

The new coding scheme complements C-PHY’s existing 6-wirestate coding scheme which transports 16 bits over seven symbols (16b7s), to provide a 2.28 bits per symbol coding factor. Use of the new 18-wirestate mode increases the maximum speed of a single C-PHY link from 13.7 Gbps using 6-wirestate mode to 17.8 Gbps using the new 18-wirestate mode, over a standard channel model. 

C-PHY v3.0 is fully compatible with previous versions of C-PHY.

MIPI C-PHY is developed by the MIPI C-PHY Working Group and is available only to MIPI Alliance members. For information about participating in MIPI Alliance, see Join MIPI.