MIPI Debug Over PCIe

The Debug Over PCIe (DO-PCIe) specification, part of the MDO family of specifications, describes methods for using the Peripheral Component Interconnect Express (PCIe) link as an interface to transport debug controls and data between a debug and test system (DTS) and a target system (TS). It provides mechanisms to perform debug of a PCIe Endpoint by using the PCIe Link and describes the communication between a DTS and a TS.

This communication is used for:

• Basic debug control, such as halt mode debugging of processors within a PCIe Device; and/or
• Tracing, where streams of data are emitted from a TS to be decoded and analyzed in a DTS.

A Debug Over PCIe system contains one or more DTS and one or more TS. TS are PCIe Endpoints including the PCIe Root Complex Integrated Endpoint (RCiEP).

Debug Over PCIe is designed in accordance with revision 6.0.1 of the PCIe specification.

The diagram below shows the standard MIPI debug architecture highlighting the functional area addressed by the Debug Over PCIe specification.

Key Capabilities

MIPI Debug Over PCIe offers key capabilities that make the interface scalable and flexible for use in applications throughout a product's lifecycle:

• Supports solutions designed to revision 2.x through 6.x of the PCIe specification
• Support for co-existence of debug and functional traffic over the PCIe link
• Support for concurrent debug of multiple PCIe devices
• Support for debug events from/to PCIe devices under debug
• Support for advertising debug capabilities in a PCIe device
• Allows debugging of any PCIe device that is addressable in a PCIe topology.
• Support for minimizing PCIe Host intervention and host resource utilization during debug session
• Supports Designated Vendor-Specific Extended Capability (DVSEC Capability) messaging and/or Memory Mapped IO Space to transfer debug data and/or messages

Diagrams & Tables

System Functional/Application Modules (click to enlarge image below)
The diagram below shows the standard MIPI debug architecture highlighting the functional area addressed by the Debug Over PCIe specification.