MIPI Debug Over UCIe

The Debug Over UCIe (DO-UCIe) specification, part of the MDO family of specifications, describes methods for using the Universal Chiplet Interconnect Express (UCIe) link as an interface to transport debug controls and data between a debug and test system (DTS) and a target system (TS). It provides mechanisms to perform debug of a UCIe-based chiplet by using either the UCIe Mainband and/or Sideband Link. It describes the communication between a DTS and a TS. This communication is used for:

• Basic debug control, such as halt mode debugging of processors within a PCIe Device; and/or
• Tracing, where streams of data are emitted from a TS to be decoded and analyzed in a DTS.

Debug Over UCIe is designed in accordance with the UCIe specifications. Initiated by the UCIe Consortium, the Debug Over UCIe specification addresses the need for high bandwidth, low-cost, closed chassis debug solution for a package containing multiple chiplets without impacting the chiplet topology. It provides a low-impact debugging solutions across chiplets within a package where the chiplets may be from different vendors.

Key Capabilities

MIPI Debug Over UCIe offers key capabilities that make the interface scalable and flexible for use in applications throughout a product's lifecycle:

• Support for co-existence of debug and functional traffic over the UCIe link
• Support for concurrent debug of multiple UCIe chiplets
• Support for debug events from/to UCIe chiplet under debug
• Support for advertising debug capabilities in a UCIe chiplet
• Utilizes and extends the UCIe Manageability Baseline and UCIe DFx Architectures

Diagrams & Tables

Debug Capabilities per Adjacent Industries »
(best viewed on desktop)

System Functional/Application Modules (click to enlarge image below)
The diagram below shows the standard MIPI debug architecture highlighting the functional area addressed by the Debug Over UCIe specification.