MIPI M-PHY®

General Info

• Overview

  MIPI M-PHY^® is a physical layer interface designed for the latest generation of flash memory-based storage and for other high-bandwidth applications that require fast communications channels. Its versatility offers engineers a range of configuration choices to connect components in a broad range of markets, including advanced 5G smartphones, wearables, PCs and large systems, such as automobiles and industrial applications.

  The specification, which uses differential signaling with an embedded clock, is optimized for applications that have a particular need for high data rates, low latency, low pin counts, lane scalability and power efficiency. Key applications include connecting flash memory-based storage and for providing chip-to-chip inter-processor communications (IPC). 

  MIPI M-PHY is developed by the MIPI PHY Working Group. The specification is available only to MIPI Alliance members. For information about joining MIPI alliance, see Join MIPI.

• Capabilities

  MIPI M-PHY has been adopted into multiple MIPI and external specifications over its long lifetime (v1.0 originally released in 2011), but today it's best known as the physical layer for UniPro, and together the two specifications have been incorporated into multiple versions of JEDEC UFS. Over the last decade, MIPI and JEDEC have enjoyed a close working relationship to share requirements and align development efforts to continue innovating UFS for the benefit of the greater storage ecosystem. 

• Latest Release

  The newest version of the specification, version 5.0, adds key features to support updates to the MIPI UniPro specification and JEDEC Universal Flash Storage (UFS) standard, making the next generation of flash memory storage even faster and more power-efficient. To satisfy climbing bandwidth requirements of the storage ecosystem, M-PHY v5.0 adds a fifth gear—"High Speed Gear 5" (HS-G5)—enabling engineers to double the potential data rate per lane to 23.32 Gigabits per second (Gbps) on one lane and 93.28 Gbps over four lanes compared with the previous specification.

  In addition, v5.0 introduces several new capabilities intended to optimize the M-PHY interface:

  • Data rates have been optimized for target applications, simplifying Phased Lock Loop (PLL) implementation and eliminating design complexity.
  • High-speed startup reduces latency, for example, when accessing flash memory on power up.
  • Eye monitoring visualizes signal health, enhancing debug functionality.
  • New attributes for equalization and other electrical updates to HS-G5 improve the suitability of M-PHY for ultra-high-bandwidth applications.

   

  Version 5.0 also streamlines the specification by making several legacy features optional and further improving latency performance and boosting power efficiency.

• Upcoming Release

  The next release of M-PHY, version 6.0, slated for release in Q4 2025, will further enhance the interface to support forthcoming updates to MIPI UniPro and JEDEC Universal Flash Storage (UFS).

  Version 6.0 introduces:

  • New high-speed gear (HS-G6), using PAM-4 signaling scheme, doubling the  bandwidth of the interface to a maximum of 46.694 Gbps per lane.
  • New 1b1b line encoding for HS-G6, improving throughput efficiency by reducing PHY coding overhead to below 10%
  • New link training option to enhance interoperability and minimize link errors. 
  • New optional link equalization feature to enable greater performance and margin per Tx/Rx.
  • Removal of 10b10b encoding and two unused legacy features: reduced amplitude mode and unshared reference clock