Physical Layer Specifications

The PHY Working Group has developed two specifications for high-speed physical layer designs to support multiple application requirements. The first specification - D-PHY - was developed primarily to support camera and display applications. The second specification - M-PHY® - supports a much broader range of applications, including interfaces for display, camera, audio, video, memory, power management and communication between Baseband to RFIC.

Complete specifications are available to MIPI members only. For more information on joining MIPI, please go to Join MIPI.

For more information on M-PHY and UniPro, MIPI Alliance’s UniPort-M solution, read the M-PHY v3.0 and UniPro v1.6 Press releaseand click here for more information—

D-PHY Specification


This specification provides a flexible, low-cost, High-Speed serial interface solution for communication interconnection between components inside a mobile device. Traditionally, these interfaces are CMOS parallel busses at low bit rates with slow edges for EMI reasons. The D-PHY solution enables significant extension of the interface bandwidth for more advanced applications. The D-PHY solution can be realized with very low power consumption.


The scope of this document is to specify the lowest layers of High-Speed source-synchronous interfaces to be applied by MIPI Alliance application or protocol level specifications. This includes the physical interface, electrical interface, low-level timing and the PHY-level protocol. These functional areas taken together are known as D-PHY.

The D-PHY specification shall always be used in combination with a higher layer MIPI specification that references this specification. Initially, this specification will be used for the connection of a host processor to display and camera modules as used in mobile devices. However, this specification can also be referenced by other upcoming MIPI Alliance specifications.

The following topics are outside the scope of this document:

  • Explicit specification of signals of the clock generator unit
  • Test modes, patterns, and configurations
  • Procedure to resolve contention situations
  • Ensure proper operation of a connection between different Lane Module types
  • ESD protection level of the IO
  • Exact Bit-Error-Rate (BER) value
  • Specification of the PHY-Protocol Interface
  • Implementations


The D-PHY specification is used by manufacturers to design products that adhere to MIPI Alliance interface specifications for mobile device such as, but not limited to, camera, display and unified protocol interfaces. Implementing this specification reduces the time-to-market and design cost of mobile devices by standardizing the interface between products from different manufacturers. In addition, richer feature sets requiring high bit rates can be realized by implementing this specification. Finally, adding new features to mobile devices is simplified due to the extensible nature of the MIPI Alliance Specifications.


M-PHY® Specification


This specification provides a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. It is targeted to be suitable for multiple protocols, including UniProSM, LLI and DigRFSM v4, and for a wide range of applications.
The M-PHY specification features the following aspects:

  • BURST mode operation for improved power efficiency
  • Multiple transmission modes with different bit-signaling and clocking schemes intended for different bandwidth ranges to enable better power efficiency over a huge range of data rates
  • Multiple transmission speed ranges/rates per BURST mode to further scale bandwidth to application needs and for mitigation of interference problems. Rates for high-speed mode are fixed, for low-speed modes they are flexible within ranges.
  • Multiple power saving modes, to allow optimization of different degrees of power consumption, offering different recovery times
  • Symbol coding (8b10b) for spectral conditioning, clock recovery, and in-band control options for both PHY and Protocol level.
  • Clocking flexibility: designed to be able to operate with independent local reference clocks at each side, but suitable to exploit the benefits of a shared reference clock
  • Optical friendly: enables low-complexity electro-optical signal conversion and optical data transport inside the interconnect between MODULEs
  • Distance: optimized for short interconnect (<10 cm) but extendable to a meter with good quality interconnect or even further with optical converters and optical waveguides.
  • Configurability: differences in supported functionality (to reduce cost) enables tuning and implementation for best performance without hampering interoperability


This specification outlines unidirectional LANEs and its individual parts, as building blocks for composition of a dual-simplex LINK by application protocols. An M-PHY implementation allows one or more LANEs in each direction, allows differences in optional funtionality between LANEs, allows different momentary operating modes between LANEs, and allows asymmetry in amount of LANEs and LANE properties for the two directions of the dual-simplex LINK. Protocols applying M-PHY technology may have different LANE constraints and choose different operation control and data striping/merging solutions. Therefore, this document provides the features to enable LINK composition, but does not specify how multiple transmitters and receivers are combined into a PHY-unit for a certain LINK composition. Each LANE has its own interface to the Protocol Layer.;

MODULEs can disclose their capabilities and do contain several configurable parameters in order to allow differentiation on supported functionality and tune for best performance without hampering interoperability. Therefore, protocols need to support some configuration mechanism to determine and define the operational settings. Most flexible is an auto-discovery negotiation protocol to determine the commonly-supported settings of the Physical Layer which are most desirable for running the application. M-PHY supports this, but does not include the configuration protocol itself. Alternatively, the protocol may directly program the required settings if there is predetermined higher system knowledge about which MODULEs are present at both ends of that LINK.

The M-PHY specification shall always be used in combination with a higher layer MIPI specification that references this specification. Any other use of the M-PHY specification is strictly prohibited, unless approved in advance by the MIPI Board of Directors.


Mobile devices face increasing bandwidth demands for each of its functions as well as an increase of the number of functions integrated into the system. This requires wide bandwidth, low-pin count (serial) and highly power-efficient (network) interfaces that provides sufficient flexibility to be attractive for multiple applications, but which can also be covered with one physical layer technology. M-PHY is the successor of D-PHY, requiring less pins and providing more bandwidth per pin (pair) with improved power efficiency.