MIPI I3C Basic in JEDEC DDR5: A Sum Greater Than Its Parts

JEDEC Solid State Technology Association (JEDEC) and MIPI Alliance have enjoyed a long liaison relationship of collaboration, as the two organizations serve some similar but also different applications and ecosystems. When we work together closely—as in development of JEDEC’s newly announced JESD79-5 DDR5 (Double Date Rate 5) standard—it results in better outcomes and broader market opportunities for all of our combined stakeholders.

The new JEDEC standard is designed to address the demand requirements of growing cloud and enterprise data center applications. According to JEDEC’s 14 July press release announcing the standard, DDR5 provides developers with twice the performance and greatly improved power efficiency.

The DDR5 system management is done using the JEDEC Module Sideband Bus Specification (JESD403), which relies on MIPI I3C Basic^SM. A subset of MIPI I3C^® that bundles the most commonly needed I3C features for developers and other standards organizations, MIPI I3C Basic is available for implementation without MIPI membership and is intended to facilitate a royalty-free licensing environment for all implementers. The mobile ecosystem and broader system integrator community can efficiently use the MIPI I3C Basic capabilities for system management in their migration from the legacy I²C.

In developing the DDR5 standard, JEDEC identified a need for higher bandwidth and throughput on the heavily loaded sideband bus. MIPI I3C Basic is ideally suited to meet these requirements, while providing backward compatibility for legacy JEDEC I²C implementations. JEDEC and MIPI already had a history of successfully collaborating to drive innovation for their diverse stakeholders. JEDEC’s Universal Flash Storage (UFS) 3.0, for example, leverages MIPI M-PHY® as its physical layer and MIPI UniPro® as its link layer. This time, MIPI and JEDEC worked together over about two years to define the JEDEC-specific additions needed in MIPI I3C Basic in areas such as compatibility, bandwidth and efficiency.

The resulting JESD403 specification forms the basic protocol layer for all DDR5 dual in-line memory module (DIMM) components. Relying on MIPI I3C Basic as the core specification with its single data rate (SDR) mode for data transfers and in-band interrupt (IBI) for power/temperature alerts and error indications, JESD403 also defines additional capabilities that can co-exist with MIPI I3C-compliant devices:

• 1.0V electrical specification to achieve 10MHz speeds in SDR mode
• SPD hub definition enabling isolation of the local bus load from host bus and achieving 10MHz speeds in a fully loaded DDR5 DIMM configuration with about 40 end points
• SETHID and SETAASA Common Command Codes (CCCs) enabling quick device/DIMM identification, enumeration and fast boot times even in maximal DDR5 DIMM configuration
• MIPI I3C IBI enabling fast power/current alerts and errors intimation, with minimal host software overhead compared to DDR4 for power management and bandwidth throttling
• Optional Packet Error Correction (PEC) codes to ensure data integrity

MIPI has adopted some of the capabilities developed for JESD403 back into the MIPI I3C v1.1 specification.

The efforts between the two organizations have resulted in extending the applicability of MIPI I3C Basic, and it allows the JEDEC DDR5 DIMM industry to leverage the MIPI I3C ecosystem, such as IPs, testers/protocol analyzers and interoperability workshops, to accelerate deployment. Host vendors also could leverage standard MIPI I3C Host Controller Interface^SM (HCI)-based IPs for enabling advanced capabilities like combo transfer, IBI auto command and time stamping to minimize software overhead and improve power and user experience.

Moreover, the successful collaboration with JEDEC shows again how developers and designers in mobile and varied other markets can access a vibrant, growing ecosystem rooted in interoperability and expand their application spaces through the MIPI Alliance.