The I3C WG is currently developing a CTS for I3C v1.1, for early 2020 release.
Each test in the I3C CTS will contain:
- A clear purpose
- Resource requirements
- Tracked last technical modification
- All test case detail (i.e., setup, procedure, results, and problems).
DC/AC parametric requirements will be embedded in each test, not split out into a separate PHY-related CTS or subsection.
Interoperability Workshops will ultimately follow the tests identified in the I3C CTS, as it nears completion.
The CTS tests are designed to determine whether a given product conforms to a subset of the requirements defined in the I3C Specification v1.0. The scope of this first version of the CTS is intentionally limited, in order to meet time-to-market requirements imposed by the rapid adoption of I3C in the marketplace, focusing on:
1. SDR-only Devices without optional I3C capabilities,
2. All Master and Slave Error Detection and Recovery methods, and
3. Basic HDR Enter/tolerance/Restart/Exit are in scope, but HDR-DDR is under consideration.
Yes. A CTS for I3C v1.0 is being drafted by the MIPI Alliance I3C WG [MIPI09].
A MIPI WG develops a Conformance Test Suite (CTS) document in order to improve the interoperability of products that implement a given MIPI interface Specification. The CTS defines a set of conformance or interoperability tests whereby a product can be tested against other implementations of the same Specification.