Why replace SPI (Serial Peripheral Interface) with I3C?

SPI requires four wires and has many different implementations because there is no clearly defined standard. In addition SPI requires one additional chip select (or enable) wire for each additional device on the bus, which quickly becomes cost-prohibitive in terms of number of pins and wires, and power. I3C aims to fix that, as it uses only two wires and is well defined.

I3C covers most of the speed range of SPI, but is not intended for the highest speed grades that really only work well with a point-to-point interface, such as for SPI Flash.

What are CCCs (Common Command Codes) and why are they used?

The CCCs are the commands that an I3C Master uses to communicate to some or all of the Slaves on the I3C Bus. The CCCs are sent to the I3C Broadcast address (which is 7’h7E) so as not to interfere with normal messages sent to a Slave. In other words, CCCs are separated from the standard “content protocol” used by normal messages, such as Private Write and Read transfers (in SDR Mode).

How can Masters and Slaves communicate on the I3C Bus?

The basic byte-based messaging schemes of I²C and SPI map easily onto I3C. Additionally, a set of common command codes (CCCs) has been defined for standard operations like enabling and disabling events, managing I3C‑specific features (e.g., Dynamic Addressing, Timing Control, etc.), and other functions. CCCs can be either Broadcasted (i.e., sent to all Devices on the I3C Bus), or else Directed at a particular Device on the I3C Bus.

Is it possible to have multiple Masters on the same I3C Bus?

Yes, I3C allows for multiple Masters on the same Bus. I3C has one Main Master that initially configures the Bus and acts as the initial Current Master. Optionally, the Bus can have one or more Secondary Master Devices that initially act as Slaves. Any Secondary Master Device can request to become the Current Master. Once the Current Master agrees to the request, and transfers Current Master control (‘Mastership’) to a given Secondary Master Device, then that Device becomes the Current Master.

What is the bit rate for I3C?

I3C has several Modes, each with associated bit rate(s). The base raw bitrate is 12.5 Mbps, with 11 Mbps real data rate at 12.5 MHz clock frequency (this is the only Mode supported in I3C v1.0 and I3C Basic v1.0). The maximum raw bitrate is 33.3 Mbps at 12.5 Mhz, with real data rate of 30 Mbps; this is achieved via HDR Modes that are currently only available in I3C v1.0.

Most traffic will use the 10 to 11 Mbps rate, while large messages can use one of the higher data rate Modes.

Is I3C backward compatible with I²C?

Yes, most I²C Slave devices can be operated on an I3C Bus, as long as they have a 50 ns glitch filter and do not attempt to stall the clock. Such use will not degrade the speed of communications to I3C Slaves; it will require decreased speed only when communicating with the I²C Slaves.

I3C Slave Devices with a Static Address can operate as I2C Slaves on an I2C bus; optionally, they can also have a 50 ns spike filter.