Debug is an essential part of any development process, and over the past two decades, the MIPI Debug Working Group has developed a rich family of debug specifications that unify the protocols and software layers for debugging ever more highly integrated embedded systems. The family of specifications, which includes MIPI Debug Over I3C℠, MIPI SneakPeek Protocol and many others, reduce development and implementation time, and ensure the interoperability of key hardware and software interfaces.
This series of four webinars will provide essential information on how to get started with MIPI debug solutions, explain why MIPI is renaming many of its debug specifications, and preview two upcoming specifications–one that will add a debug security layer and another that will enable MIPI debug over UCIe transport links.
Aimed at engineers who would like to get started with MIPI debug solutions, this session will introduce the MIPI debug working group's charter (scope of work) and explain the current focus areas of the group, which include the development of the MIPI security specification for debug and MIPI debug over UCIe specification (both of which have their own dedicated sessions within the webinar series). After this introduction, this session will provide an overview of the approach the working group has taken to develop an overarching MIPI debug system framework, explaining how the framework breaks down modern system-on-chip (SoC) debug architectures into manageable debug subsystems by applying a layering approach to the debug system stack. The session will conclude with a brief introduction to all of the current debug specifications and provide a brief preview of upcoming specifications.
Debug is a critical feature of any system, and debug capabilities, if not properly protected, could potentially be used by adversaries to gain access to cryptographic keys, private data and other sensitive assets. To support the need to protect debug and trace features, a new MIPI security specification, targeted for release in 2025, will add an optional security layer to the MIPI "Debug Over" family of specifications.
This presentation will provide a preview of the forthcoming MIPI security specification for debug and explain the approach taken within the MIPI debug architecture to add a security layer. It will explain what is in (and out) of scope of the security layer, covering requirements for secure session management, key negotiation (leveraging recommended industry standards), message encryption and authentication, and secure message formats. The session will explain how the forthcoming security specification for debug follows a similar approach to the recently adopted MIPI Camera Security Framework by leveraging the DMTF’s Security Protocols and Data Models (SPDM) specification as its basis.
In 2024, MIPI began to transition the names of several longstanding MIPI debug specifications to create a new family of “MIPI Debug Over” (MDO) specifications. MIPI Debug Over I3C was the first of the debug interfaces to officially make this transition, and several other existing debug specifications will transition to the new naming scheme in their next updates.
This webinar will introduce the "MIPI Debug Over" (MDO) family of specifications, explaining why MIPI has chosen to move away from the speed-centric “Gigabit Debug”-type naming schemes of the past. The session will take a deep dive into the new family of MDO specifications, explaining how they are based on a common layered stack architecture that enables a flexible underlying debug infrastructure that can be transmitted over different transports links, providing scalability and ease of adoption. The session will highlight the use of existing transports links supported by the MDO specifications today (including USB and I3C) and give a preview of upcoming new links (such as PCIe and UCIe) that will be added to the MDO family in the near future.
UCIe™ (Universal Chiplet Interconnect Express™) is an open specification that defines the interconnect between chiplets within a System-In-Package (SiP), enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
To support this initiative, MIPI will extend its MIPI "Debug Over" family of specifications to include the UCIe transport. Targeted for completion in 2026, the new specification will enable the debugging of UCIe chiplets that are addressable over a UCIe-based topology within a SiP. The specification will leverage UCIe defined Management Transport infrastructure for debugging UCIe chiplets using MIPI defined standard debug protocols such as MIPI SneakPeek Protocol (SPP℠), MIPI System Trace Protocol (STP℠), and MIPI Trace Wrapper Protocol (TWP℠).
This presentation will provide a preview of the forthcoming specification, explaining how it will support debug over UCIe in various Debug and Test System (DTS) and Target System (TS) configurations. The presentation will explain the detection, configuration, and collection of debug data from the UCIe chiplets in a SiP.