MIPI Debug for I3CSM, which is currently under development, is a bare-metal, minimal-pin interface for transporting debug controls and data between a debug and test system (DTS) and a target system (TS). Current debug solutions, such as JTAG and ARM® Serial Wire Debug, are statically structured which leads to limited scalability regarding the accessibility of debug components/devices. Also, when looking at the new requirements of near future technologies, such as 5G, and environments/markets, such as IoT, there are gaps that need to be addressed. MIPI Debug for I3C targets these gaps and shortcomings by using the capabilities of I3C to handle debug connectivity on buses that are dedicated for debug or shared with functional transfers, handling the debug network topology in a dynamic fashion.
The main capabilities for the MIPI Debug for I3C Specification are:
- Debug over 2 pins
- Single ended
- Push pull / open drain
- Native I3C communication
- Multi-master capable
- Multi-drop capable
- Use of generic CCCs to include debug devices e.g., hot join
- Dedicated debug CCC to encapsulate debug messaging
- Event indication and detection via the in band interrupt method.
- Debug and event capable slaves are able to passively detect debug IBIs
- DTS implemented as bus master
- Main or secondary
- May act as bus slave to become a trace sink
MIPI Debug for I3C is being developed by the MIPI Debug Working Group and is currently expected to be released in 2020.