General Info

MIPI I3C^® is a scalable, medium-speed, utility and control bus interface for connecting peripherals to an application processor, streamlining integration and improving cost efficiencies. It gives developers unprecedented opportunities to craft innovative designs for any mobile product—from smartphones, to wearables, to systems in automobiles.

Designed as the successor of I2C, MIPI I3C incorporates key attributes of the traditional I²C and SPI interfaces to provide a unified, high-performing, very-low-power solution and delivers a robust, flexible upgrade path to I3C for I²C and SPI implementers. While I3C v1.0 delivered new capabilities to integrate mechanical, motion, biometric, environmental and any other type of sensor, updates to the specification have added new features for peripheral command, control and communication to a host processor over a short distance and system manageability.

MIPI I3C is developed by the MIPI Alliance I3C Working Group. The full I3C specification is available only to MIPI Alliance members, and a public version, I3C Basic, is available to non-members (see below). For information about joining MIPI Alliance, visit Join MIPI.

Implementation

MIPI I3C technology is implemented on a standard CMOS I/O. It uses a two-wire interface and supports in-band interrupts which reduces pin count and signal paths to offer system designers less complexity and more flexibility. It can also be used as an efficient sideband interface to, for example, replace the use of GPIOs, to further reduce pin count. MIPI I3C supports a typical data rate of 11.1 Megabits per second (Mbps) with options for higher-performance high-data-rate modes up to 100Mbps , offering a substantial leap in performance and power efficiency compared with previous options.

The specification enables a diverse set of applications:

• Sensor and actuator device command, control and data transport
• "Always-on" imaging
• Memory sideband channel
• Server system management
• Debug application communications
• Power management

The specification is ideal for system-level implementers seeking a low-cost, off-the-shelf standardized bus solution with a small printed circuit board (PCB) footprint and a well-defined and readily available ecosystem of peripherals, sensors and applications.

To support developers, I3C device compatibility and legacy I2C device coexistence has been confirmed through multiple interoperability workshops, and two supporting specifications—DisCo for I3C™ and the I3C Host Controller Interface (MIPI I3C HCI™)—have been made publicly available. Further, an I3C HCI driver has been added to the Linux kernel, and a Debug for I3C specification was released in 2020.

Performance Highlights

Additional technical highlights include multi-controller support, dynamic addressing, command-code compatibility and a uniform approach for advanced power management features, such as sleep mode. It provides synchronous and asynchronous time-stamping to improve the accuracy of applications that use signals from various sensors. It can also batch and transmit data quickly to minimize energy consumption of the host processor.

Latest Release

The most recent specification, I3C v1.2, rearranges the document to make it modular, to clearly identify mandatory and optional features, reduce ambiguity, and allow easier updating of future versions. Whilst I3C v1.2 does not introduce any new features, it does incorporate the two Erratas for I3C v1.1.1, and adds several important clarification on the use of existing features, including dynamic address management, target reset behavior, HDR CCC flows, timing parameters, maximum message lengths, error reset and error recovery.

MIPI I3C Basic

MIPI I3C Basic™ is a subset of MIPI I3C that bundles the most commonly needed I3C features for developers and other standards organizations. The mobile ecosystem and broader system integrator community can efficiently use these capabilities as an alternative to I2C.

MIPI I3C Basic is available for implementation without MIPI membership and is intended to facilitate a royalty-free licensing environment for all implementers, as described within the specification.

The most recent version of I3C Basic dramatically enhances the specification’s speed and flexibility. I3C Basic v1.1.1 provides for extensible use of extra bus lanes to increase the interface speed to near 100 Mbps. This version includes two High Data Rate (HDR) modes—HDR Double Data Rate (HDR-DDR) and HDR Bulk Transport (HDR-BT)—designed to transfer more data at the same bus frequency. Another feature, standardized target reset, improves I3C Basic’s ability to reset a specific peripheral device, enabling better recovery from error conditions. I3C Basic v1.1.1 also replaces offensive terms with ones that more accurately reflect the functions of technical devices.

The specification is developed by the MIPI I3C Basic Ad Hoc Working Group.