You're invited to join us on 27-29 November for MIPI's Camera Week webinar series–two webinars exploring the system architecture implications of using MIPI CSI‑2® over C‑PHY℠ and D‑PHY℠, and a member use case on how CSI-2 can deliver optimum image quality in notebook products.
Led by developers and implementers of CSI-2, D-PHY and C-PHY, this webinar series offers the opportunity to dive deeper into CSI-2 features and PHY-specific system considerations, engage with experts through live Q&A sessions, and gain insights from a real-world implementation experience.
Save your spot at all three webinars with a one-time registration.
The week kicks off on Monday, 27 November (8-9 a.m. PST), with "An Exploration of MIPI CSI‑2 over D‑PHY Imaging System Design Considerations," presented by Haran Thanigasalam, MIPI camera and imaging consultant, and Raj Kumar Nagpal, chair of the MIPI D-PHY Working Group.
The presentation will provide an overview of key CSI-2 features, including Latency Reduction and Transport Efficiency (LTRE), Scrambling, Unified Serial Link (USL), Differential Pulse Code Modulation (DPCM), and Multi-Pixel Compression (MPC). It will also explore CSI-2 over D-PHY imaging system design considerations, with focus on support for higher channel rates, SoC port/pin optimization and lower RF emissions. In addition, presenters will address design considerations in conjunction with upcoming D-PHY developments, including the continued introduction of an embedded clock option.
On Wednesday, 29 November, 8-9 a.m. (PST), Haran will be joined by George Wiley, chair of the C-PHY Working Group, for "An Exploration of MIPI CSI-2 over C-PHY Imaging System Design Considerations." This webinar will also look at CSI-2 features, in this case, the “Always On Sentinel Conduit” for ultra-low power vision inferencing and “Smart Region Of Interest” to enable smarter image sensors. Following a closer look at both current and forward-looking CSI-2 over C-PHY imaging system design considerations, with a focus on support for higher channel rates and SoC port/pin optimization, the presenters will discuss upcoming C-PHY developments such as the introduction of a new multi-phase coding scheme.
Also on Wednesday, 29 November, 5 p.m. (PST) (10 a.m. (JST) on 30 November), MIPI will welcome Xueyong Yang, hardware engineer in system design strategy at Lenovo Japan, for his presentation on "Delivering the Best Camera Image Quality Using MIPI Interfaces on ThinkPad Notebook." Xueyong will discuss Lenovo's approach to providing customers with a “best-in-class” video conference experience in a notebook environment by utilizing MIPI camera interfaces combined with powerful image signal processing capabilities integrated into a SoC.