Unlike I²C, there is no natural way to ‘hang’ the bus. In I²C, clock stretching (where the Slave holds the clock low, stopping it from operating) often causes serious problems with no fix: there’s simply no way to get the Slave’s attention if it has hung the bus. By contrast, in I3C only the Master drives the clock, and so the Slave performs all actions on SDA relative to that clock, thereby eliminating the normal causes of such hangs.
Further, since I3C is designed to ensure that I3C Slaves can operate their back-end I3C peripheral off the SCL clock (vs. oversampling), problems elsewhere in the Slave will not translate into bus hangs.
If a system implementer is highly concerned about a Slave accidently locking itself, then a separate hard reset line could be used. For the next revision of the I3C and I3C Basic Specifications, a feature called Slave Reset is being added to reset non-responsive I3C Slaves (i.e., if a Master emits a certain pattern that does not occur during regular communication, then the devices on the bus would treat it just like a hardwired reset line).